Merge requests · FPGA Firmware / Modules / Board Support Packages (BSP) / bsp_fmc1z7io

fix: remove gap in IRQ assignment to PS

!9 · created Apr 19, 2024 by Michael Buechler
- Merged
- 3
updated May 06, 2024
feat: parse the BSP's VHDL constants in Tcl

!8 · created Apr 15, 2024 by Michael Buechler
- Merged
- 3
- Approved
updated Jul 10, 2024
refactor: clock for AXI buses is from PL osc, add reset tree conf

!7 · created Mar 06, 2024 by Michael Buechler
updated Mar 18, 2024
fix: pass the full address on the app register interface

!6 · created Mar 06, 2024 by Michael Buechler
- Merged
updated Mar 06, 2024
refactor!: cleanup and refactore of the code

!5 · created Jan 29, 2024 by Lukasz Butkowski
- Merged
- 12
- Approved
updated Feb 07, 2024
Adapt for PCIe x4

!4 · created Jan 16, 2024 by Michael Buechler
- Merged
updated Jan 16, 2024
fix: Use correct DIFF_TERM settings on clock inputs

!3 · created May 10, 2023 by Cagil Guemues
- Merged
- 1
- Approved
updated May 30, 2023
feat: add an I2C controller for the MMC mailbox

!2 · created Apr 13, 2023 by Cagil Guemues
- Merged
- 1
updated Apr 13, 2023
BSP initial implementation

!1 · created Jun 10, 2022 by Cagil Guemues
- Closed
- 1
updated Mar 29, 2023