fix: Use correct DIFF_TERM settings on clock inputs

The schematics tell which differential clock inputs have external termination resistors and which do not. Apply this to the constraint files.

External termination resistors are necessary when the FPGA cannot use its internal termination at the given IO standard. This is the case for IO banks 34 and 35 which use an adjustable bank voltage of 1.2V-1.8V. At 1.2V the internal termination is not available.