pcie40_b2slc.h

#ifndef PCIE40_B2SLC_H
#define PCIE40_B2SLC_H
// Header file for B2 Slow control functions with PCIe40 

// Constants
// BAR number for Slow control interface
#define SLC_BAR 2
// Address of the register to reset the write FIFO and bit to use
#define SLC_WFIFO_RESET_ADD 0x00050100
#define SLC_WFIFO_RESET_BIT 8
#define SLC_WFIFO_EMIT_BIT 0
#define SLC_WFIFO_ADD 0x00050000
#define SLC_RFIFO_STATUS 0x00050160
#define SLC_RFIFO_ADD 0x00050140

// Functions to read/write registers and stream files to Front End

int pcie40_readfee8(int fd, int adr);

int pcie40_writefee8(int fd, int adr, int val);

int pcie40_readfee32(int fd, int adr, int *valp);

int pcie40_writefee32(int fd, int adr, int val);

int pcie40_writestream(int fd, char *filename);

#endif // PCIE40_B2SLC_H