First prototype of slow control libs

Pcie40Libraries/pcie40_b2slc.c

+// File for Belle2 slow control access with PCIe40 
+
+/* ---------------------------------------------------------------------- *\
+   readfee8
+   returns -1 in case of error
+\* ---------------------------------------------------------------------- */
+int pcie40_readfee8( int dev , int adr) {
+  // PCIe40
+  if ( ( adr <=0 ) || ( adr >= 0x7F ) ) return -1 ;
+  // Reset the FIFO
+  unsigned ret = 0 ;
+  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
+  if ( ret != 0 ) return -1 ;
+  // Fill the FIFO with the requested information
+  uint_64 data_word = 
+    ( 0x73 ) | ( 0x07 << 8 ) | ( adr << 16 ) | ( 0x0c << 32 ) | ( 0x08 << 40 ) ;
+  // (temporary : 32 bits only)
+  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word & 0xFFFFFFFF ) ) ;
+  if ( ret != 0 ) return -1 ;
+
+  // Wait for the result to come back
+  int i ;
+  for ( i=0 ; i<10 ; i++ ) {
+    usleep( 10 ) ; //10 ms
+    ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS ) ;
+    if ( ret == 0x11 ) break;
+  }
+
+  if (i == 10) return -ETIME;
+
+  // Read the value 
+  ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
+
+  return ret;
+}

Pcie40Libraries/pcie40_b2slc.h

+#ifdef PCIE40_B2SLC_H
+// Header file for B2 Slow control functions with PCIe40 
+
+// Constants
+// BAR number for Slow control interface
+#define SLC_BAR 2
+// Address of the register to reset the write FIFO and bit to use
+#define SLC_WFIFO_RESET_ADD 0x000500000
+#define SLC_WFIFO_RESET_BIT 2
+#define SLC_RFIFO_STATUS 0x00000
+#define SLC_RFIFO_ADD 0x0000
+
+// Functions to read/write registers and stream files to Front End
+
+int pcie40_readfee8(int fd, int adr);
+
+int pcie40_writefee8(int fd, int adr, int val);
+
+int pcie40_readfee32(int fd, int adr, int *valp);
+
+int pcie40_writefee32(int fd, int adr, int val);
+
+int pcie40_writestream(int fd, char *filename);
+
+#endif // PCIE40_B2SLC_H
+