slc:

.gitignore

@@ -25,5 +25,6 @@ module.target
 modules.order
 Pcie40Applications/pcie40_ecs
 Pcie40Applications/pcie40_reload
+Pcie40Applications/pcie40_b2slc
 *.d
 **/pcie40_reload.out

Pcie40Applications/Makefile

@@ -21,12 +21,19 @@ PCIE40_RELOAD :=pcie40_reload
 PCIE40_RELOAD_LINK =$(SCRIPTS_INSTALL)/pcie40_reload_suid
 PCIE40_RELOAD_INSTALL =$(PREFIX)/bin
 
+PCIE40_SLC :=pcie40_b2slc
+PCIE40_SLC_OBJS =main_pcie40_b2slc.o
+PCIE40_SLC_CFLAGS =$(CFLAGS) -I$(TOP) -I$(TOP)/../Pcie40Libraries
+PCIE40_SLC_INSTALL =$(PREFIX)/bin
+PCIE40_SLC_LDFLAGS = -L../Pcie40Libraries/lib -lpcie40 -L../Pcie40DriverLibraries/ -lpcie40driver_ecs
+
 VPATH :=$(TOP)
 
 include $(TOP)/rules.mk
 
 ifeq ($(ENABLE_PCIE40), true)
 $(eval $(call ODIR_template,PCIE40_ECS))
+$(eval $(call ODIR_template,PCIE40_SLC))
 $(eval $(call COPY_template,SCRIPTS,755))
 $(eval $(call LINK_template,PCIE40_RELOAD))
 $(eval $(call ODIR_template,PCIE40_RELOAD_SUID))

Pcie40Applications/main_pcie40_b2slc.c

+int main(int argc, char *argv[]) { 
+
+  ecs_open( 0 , 2 ) ;
+
+  pcie40_readfee8( 0 , 0x10 ) ;
+  
+  ecs_close( 0 , 2 ) ;
+
+
+  return 0 ;
+}

Pcie40Libraries/Makefile

@@ -27,14 +27,20 @@ MINIPODS_OBJ=$(MINIPODS_SRC:%.c=$(OBJ_DIR)%.o)
 LTC2990_SRC= 
 LTC2990_OBJ=$(LTC2990_SRC:$(SRC_DIR)$(LTC2990_DIR)%.c=$(OBJ_DIR)%.o)
 
+# Belle II slow control library 
+B2SLC_SRC= pcie40_b2slc.c 
+B2SLC_OBJ=$(B2SLC_SRC:%.c=$(OBJ_DIR)%.o)
+
 # static libraries
 ECS_LIB= libecs.a
 MINIPODS_LIB= libminipods.a
 LTC2990_LIB= libltc2990.a
+B2SLC_LIB = libb2slc.a
+
 # dynamic libraries
 LLI_DYNLIB= libpcie40.so
 
-all: $(ECS_OBJ) $(ECS_LIB) $(MINIPODS_OBJ) $(MINIPODS_LIB) $(LTC2990_OBJ) $(LTC2990_LIB) $(LLI_DYNLIB)
+all: $(ECS_OBJ) $(ECS_LIB) $(MINIPODS_OBJ) $(MINIPODS_LIB) $(LTC2990_OBJ) $(LTC2990_LIB) $(B2SLC_LIB) $(LLI_DYNLIB)
 
 $(ECS_OBJ): $(OBJ_DIR)%.o : %.c
 	@echo "Construction of ecs objects $@ from $<"
@@ -47,6 +53,17 @@ $(ECS_LIB) : $(ECS_OBJ)
 	ar -q $(LIB_DIR)$(ECS_LIB) $(ECS_OBJ)
 	@echo ""
 
+$(B2SLC_OBJ): $(OBJ_DIR)%.o : %.c
+	@echo "Construction of ecs objects $@ from $<"
+	mkdir -p obj
+	$(CC) $(CFLAGS) -I . -I $(PCIE40_INC_DIR)  $< -o $@	
+
+$(B2SLC_LIB) : $(B2SLC_OBJ)
+	@echo "Construction of Belle II SLC Library"
+	mkdir -p lib
+	ar -q $(LIB_DIR)$(B2SLC_LIB) $(B2SLC_OBJ)
+	@echo ""
+
 $(MINIPODS_OBJ): $(OBJ_DIR)%.o : $(SRC_DIR)%.c
 	@echo "Construction of $@ from $<"
 	$(CC) $(CFLAGS) -I . -I $(INC_DIR)$(SYSTEM_DIR) -I $(PCIE40_INC_DIR) $< -o $@
@@ -70,7 +87,7 @@ $(LTC2990_LIB) : $(LTC2990_OBJ)
 $(LLI_DYNLIB) : $(ECS_OBJ) $(MINIPODS_OBJ)
 	@echo "Construction of dynamic LLI technical Library for V2"
 	mkdir -p lib
-	$(CC) -o $(LIB_DIR)$(LLI_DYNLIB) -shared $(ECS_OBJ) $(PLL_OBJ) $(MINIPODS_OBJ) -L $(PCIE40_DYN_LIB) -lpcie40driver_ecs
+	$(CC) -o $(LIB_DIR)$(LLI_DYNLIB) -shared $(ECS_OBJ) $(PLL_OBJ) $(MINIPODS_OBJ) $(B2SLC_OBJ) -L $(PCIE40_DYN_LIB) -lpcie40driver_ecs
 	@echo 
 
 clean: mrproper

Pcie40Libraries/pcie40_b2slc.c

 // File for Belle2 slow control access with PCIe40 
+#include "pcie40_b2slc.h"
+#include <unistd.h>
+#include "pcie40_ecs.h"
 
 /* ---------------------------------------------------------------------- *\
    readfee8
@@ -12,10 +15,11 @@ int pcie40_readfee8( int dev , int adr) {
   ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
   if ( ret != 0 ) return -1 ;
   // Fill the FIFO with the requested information
-  uint_64 data_word = 
-    ( 0x73 ) | ( 0x07 << 8 ) | ( adr << 16 ) | ( 0x0c << 32 ) | ( 0x08 << 40 ) ;
+  int data_word_1 = 
+    ( 0x73 ) | ( 0x07 << 8 ) | ( adr << 16 ) | ( 0x0c << 24 ) ;
+  int data_word_2 = ( 0x08 << 0 ) ;
   // (temporary : 32 bits only)
-  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word & 0xFFFFFFFF ) ) ;
+  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word_1 & 0xFFFFFFFF ) ) ;
   if ( ret != 0 ) return -1 ;
 
   // Wait for the result to come back
@@ -26,10 +30,26 @@ int pcie40_readfee8( int dev , int adr) {
     if ( ret == 0x11 ) break;
   }
 
-  if (i == 10) return -ETIME;
+  if (i == 10) return -1;
 
   // Read the value 
   ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
 
   return ret;
 }
+
+int pcie40_writefee8( int dev , int adr , int val ) {
+  return 0 ;
+}
+
+int pcie40_readfee32( int dev , int adr , int *valp ) {
+  return 0 ;
+}
+
+int pcie40_writefee32( int dev , int adr , int val ) { 
+  return 0 ;
+}
+
+int pcie40_writestream( int dev , char * filename ) {
+  return 0 ;
+}

Pcie40Libraries/pcie40_b2slc.h

-#ifdef PCIE40_B2SLC_H
+#ifndef PCIE40_B2SLC_H
+#define PCIE40_B2SLC_H
 // Header file for B2 Slow control functions with PCIe40 
 
 // Constants
@@ -7,6 +8,7 @@
 // Address of the register to reset the write FIFO and bit to use
 #define SLC_WFIFO_RESET_ADD 0x000500000
 #define SLC_WFIFO_RESET_BIT 2
+#define SLC_WFIFO_ADD 0x00000010
 #define SLC_RFIFO_STATUS 0x00000
 #define SLC_RFIFO_ADD 0x0000