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feat: Gen.3 power-on self test (#11192)

Martin Christoph Hierholzer requested to merge mhier/wip-sprint-2023-autumn into master

Tests for presence of hardware patch wire which is part of the Gen.3 interlock scheme. The patch wire forces the DAC to be cleared while a (latched) interlock signal is present. The P.O.S.T. will check that driving the DAC at boot time does not result in a significant readback value at the ADC.

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