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Cleanup

Cagil Guemues requested to merge cleanup into a7_m2s

Changelog:

  • MLVDS S2M clock detection now relies on the main 125MHz aurora clock, (NO HARDWARE TESTS DONE, ONLY PROVEN ON SIMULATION)
  • remove debug attributes from the overall project
  • Make sure VIO shows signal names on the Vivado Hardware Manager
  • Remove MLVDS Enable VIO output. MLVDS transceivers are now enabled as soon as FPGA wakes up

Merge request reports

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