The index of the buffer to be written (active buffer) alternates when the transaction is completed (buffer is full). Pulse ID (which will be associated with the new inactive buffer) should be captured while switching the buffers.

feat(rdl): ENABLE and DUB_BUF_ENA registers should be 2D in order to prevent race conditions when two separate server instances want to control DAQ regions

fix: minimum value for the almost empty threshold, remove unnecessary function for almost full threshold

With an AXI burst length of 4 on the DSBAM (Zynq Ultrascale+) the FIFO_STATUS registers started counting like crazy after programming the bitstream without DAQ regions enabled. It turned out that for the burst length of 4 the value for the almost full threshold of the FIFOs in the DAQ is set to 0, which led to the FIFO18E2 cells already setting the flag after the reset.

I suspect that the value 0 was not intended as a threshold. In any case, the DAQ works with this change. We should discuss whether this approach is correct or whether I have misunderstood something here.

feat: add done port for each region at top

See merge request !4

merging fixes and feat: CDC, doc, buffer start output

See merge request !3

# Conflicts:
#   tcl/main.tcl

* Might be used to trigger interruption on buffer switch

* Typo in constant name and precise type for natural array.

* Remove logic and on async reset: it is reclocked in top level.
* Use the cdc_sync from the desy vhdl library.
* Avoid timing failure by setting false paths on 'reg_metastable'.
* Avoid timing failure by setting false paths on 'areset_n'.

* pkg_common_numarray is required.

workaround will be configuring interfaces with larger ID

as a consequence of this workaround right-aligned axi transaction id from daq_to_axi become left-aligned after axi4_mux

Desyrdl integration

See merge request !2

Michael Buechler authored 3 years ago and Lukasz Butkowski committed 3 years ago

The DesyrDL integration needs a name here for the generated .rdl
content.