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FPGA Firmware
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Miscellaneous Modules (MISC)
daq
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Tags give the ability to mark specific points in history as being important
2.1.0
229b876f
·
fix(desyrdl): use dedicated port to reset the bus
·
Oct 25, 2023
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2.0.0
160c492c
·
Merge branch 'desyrdl_integration' into 'main'
·
Sep 06, 2022
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1.1.0
abb0a9f7
·
Increased maximum AXI width to 512, removed DPM from the setSources
·
Jun 30, 2021
2021 winter shutdown
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1.0.0
de010070
·
Added lightweight Python API to scripts folder
·
Feb 19, 2021
Release:
1.0.0
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0.1.0
177a970b
·
Added skeletons, ported documentation from Redmine
·
Feb 11, 2021
Taken from SVN at revision r4366
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