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bsp_sis8300ku
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master
d3a863fb
·
build: do not escape if tool is not Vivado, 'if' is present
·
Feb 09, 2022
review_lb
8c734498
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refactor!: corrected file naming, axi port names, bsp reset
·
Apr 01, 2022
ddr_init
150dfca2
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fix: ddr_calib_done signal size
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Apr 11, 2022
desy_vhdl_switch
c83af718
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fix(addr): change addresspace generation to new FWK style
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Aug 31, 2022
aurora
5bd6642b
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fix: libraries with same name but different VHDL revision are physically...
·
Sep 02, 2022
lll
840ab062
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build: add bsp configuration for 81 MHz app clock
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Mar 27, 2023
feat/si5326
0ab572df
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WIP: SI5326 support added IO constraints
·
Oct 06, 2023