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bsp_sis8300ku
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e99f0477
·
fix(
5f49bb5f
): update VHDL after rdl fix
·
Apr 09, 2024
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d3a863fb
·
build: do not escape if tool is not Vivado, 'if' is present
·
Feb 09, 2022
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review_lb
8c734498
·
refactor!: corrected file naming, axi port names, bsp reset
·
Apr 01, 2022
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ddr_init
150dfca2
·
fix: ddr_calib_done signal size
·
Apr 11, 2022
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desy_vhdl_switch
c83af718
·
fix(addr): change addresspace generation to new FWK style
·
Aug 31, 2022
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aurora
5bd6642b
·
fix: libraries with same name but different VHDL revision are physically...
·
Sep 02, 2022
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