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Dmytro Levit
Software
Commits
bc75564b
Commit
bc75564b
authored
5 years ago
by
Patrick Robbe
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Update for 4 link version
parent
f81adfd8
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2 merge requests
!6
Master
,
!8
6links slc tool
Changes
1
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1 changed file
Python/components/fpga_comp.py
+9
-9
9 additions, 9 deletions
Python/components/fpga_comp.py
with
9 additions
and
9 deletions
Python/components/fpga_comp.py
+
9
−
9
View file @
bc75564b
...
@@ -552,39 +552,39 @@ class Arria10(object):
...
@@ -552,39 +552,39 @@ class Arria10(object):
return
json
.
loads
(
string
)
return
json
.
loads
(
string
)
def
runNumber
(
self
):
def
runNumber
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
18
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
02
0
)
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
def
triggerTag
(
self
):
def
triggerTag
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
1C
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
04
0
)
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
def
clockUp
(
self
):
def
clockUp
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x800
)
>>
11
return
(
val
&
0x800
)
>>
11
def
ttdUp
(
self
):
def
ttdUp
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x1000
)
>>
12
return
(
val
&
0x1000
)
>>
12
def
triggerType
(
self
):
def
triggerType
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x1E000
)
>>
13
return
(
val
&
0x1E000
)
>>
13
def
triggerCounter
(
self
):
def
triggerCounter
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x1FFE0000
)
>>
17
return
(
val
&
0x1FFE0000
)
>>
17
def
rxReady
(
self
):
def
rxReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x1
)
>>
0
return
(
val
&
0x1
)
>>
0
def
txReady
(
self
):
def
txReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x2
)
>>
1
return
(
val
&
0x2
)
>>
1
def
b2linkReady
(
self
):
def
b2linkReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
12
0
)
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050
00
0
)
return
(
val
&
0x4
)
>>
2
return
(
val
&
0x4
)
>>
2
def
resynchronizeLink
(
self
):
def
resynchronizeLink
(
self
):
...
...
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