Create pll lock file when loading the driver

Pcie40Applications/pcie40_reload.sh

@@ -139,6 +139,9 @@ fi
 
 # Remove pll lock file for pll_status_small
 sudo rm -f /tmp/pcie40_pll_lockfile.lck
+# create a new one and give permission to all
+sudo touch /tmp/pcie40_pll_lockfile.lck
+sudo chmod 777 /tmp/pcie40_pll_lockfile.lck
 
 #ug`pcie40_reload.steps`2
 # . For every PCIe40 interface:

Scripts/testSLC.py

@@ -25,7 +25,7 @@ for i in xrange( args.N ):
     data = random.randint( 0 , 0xFFFFFFFF )
     lli.pcie40_writefee32( 0 , args.channel , address[ args.detector ] , data )
     result = slc_read( 0 , args.channel , address[ args.detector ] )
-    if i%1000 == 0:
+    if i%10000 == 0:
         print(str(i))
     if result != data:
         print("mismatch between write ({0:X}) and read ({1:X})".format( data , result ))