pixel counters readout block

This merge request introduces the pixel counter readout. It is made of two additions:

• The readout_block that connects to the pattern generator and the FIFO
• The FIFO which connects to the readout_block and to corresponding AXI registers

The readout_block implements a readout state machine that issues read request to the chip in order to read the matrix column data. This request is issued for the 64 columns. At each request, the state machine waits for the read transaction to start and finish, retrieves the 4 * 32b words where each 8b word corresponds to a single pixel counter, and writes the 32b words into the FIFO.

The FIFO write is controlled by the readout_block, the FIFO read is controlled via an AXI register and thus from software. The counter data is redirect to a single 32b AXI register that will have to be read multiple times in order to retrieve all the matrix data.