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Jiri Kvasnicka
CALICE-DIF2-fw
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ClockGating
5b84c4b5
·
major update of the clock (removed the async 5 MHz distribution inside FPGA)...
·
Feb 22, 2018
PhaseTuning
a6a6171f
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created branch for DIF phase tuning
·
Mar 22, 2018
ShiftedAdcPower
1b1d67de
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added binaries
·
May 11, 2018
ILC_mode
1e555ff9
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fixed zynq power consumption - proper sleep
·
Jul 20, 2018
master
default
protected
41f7243a
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merged with shifted adc power to the start of the acquisition in PP mode
·
Nov 08, 2018
DutyCycle
14d0b98c
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updated blink code to 20181113
·
Nov 13, 2018
Retiming
fe7bdd57
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timing adjustments. steering parameters for timing added.
·
May 17, 2019