Interrupt tree with deviceaccess

This change implements interrupts with interrupt tree possibilities and connection to ChimeraTK over proper map file generation.

It is possible to set intr property for the register. It will generate proper VHDL register and it will add meta data into map files.

It base on SystemRDL specification.

Added property not defined in spec:

• desyrdl_intr_line - defines to which interrupt line current interrupt is connected. (in xdma it defines the event file). SystemRDL assumes only one interrupt line on top. This value has to follow VHDL connection. This propagates into map file. If not set default value is 0.

Interrupt with no tree.

ISR in application. Example SystemRDL file:

  reg {
      desc = "Interrup Status Register.";
      default sw = rw;
      default hw = w;
      default woclr; // Clear is via writing a 1
      field { desc = "Report trigger."; posedge intr; } trigger[1] = 0x00;
  } ISR ;

  reg {
      desc = "Interrup Enable Register.";
      default sw = rw;
      default hw = r;
      field { desc = "Enable trigger interrupt."; } trigger[1] = 0x00;
  } IER ;

In VHDL:

    -- connect enables - DesyRDL no referce support, needed in VHDL
    addrmap_i.ISR.trigger.enable  <= addrmap_o.IER.trigger.data;
    -- signals to int connections
    addrmap_i.ISR.trigger.intr         <= trg_main;

    -- assign out interrupt line, TOP interrupt e.g. in PCIe
    po_irq_req(0) <= addrmap_o.ISR.intr; -- desyrdl_intr_channel = 0

Interrupt tree.

It is possible to connect interrupts over modules tree.

Example DAQ has ISR register and it is connected to APP ISR. There is added daq filed to ISR register. This interrupt has to be non sticky type.

SystemRDL:

  
  reg {
      desc = "Interrup Status Register.";
      default sw = rw;
      default hw = w;
      default woclr; // Clear is via writing a 1
      field { desc = "Report trigger."; posedge intr; } trigger[1] = 0x00;
      field { desc = "Report daq"; nonsticky intr;} daq[1];
  } ISR ;

  reg {
      desc = "Interrup Enable Register.";
      default sw = rw;
      default hw = r;
      field { desc = "Enable trigger interrupt."; } trigger[1] = 0x00;
      field { desc = "Enable DAQ module interrupt."; } daq[1] = 0x0;
  } IER ;

  daq DAQ;

  ISR.daq->next = DAQ.ISR->intr;

In VHDL:

    -- connect enables - DesyRDL no referce support, needed in VHDL
    addrmap_i.ISR.trigger.enable  <= addrmap_o.IER.trigger.data;
    -- signals to int connections
    addrmap_i.ISR.trigger.intr         <= trg_main;
   -- tree connections po_irq_req from DAQ module connects here
    addrmap_i.ISR.daq.intr(0)    <= daq_irq;
    -- assign out interrupt line, TOP interrupt e.g. in PCIe
    po_irq_req(0) <= addrmap_o.ISR.intr; -- desyrdl_intr_channel = 0

Closes #5 (closed)