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Interrupts support

Lukasz Butkowski requested to merge interrupts into main

Implementation of interrupt register based on SysteRDL 2.0 specification and examples.

1. Interrupt assignment to intr register in VHDL:

-- one bit interrupt field
addrmap_i.ISR.trigger.intr(0) <= trigger;

For now DesyRDL does not support reference assignments in SystemRDL so all the connections over reference as in example has to be done in in VHDL.

2. Due to above fact we also limit to have only enable property, not mask and enable. Mask property can be achieved by not enable signal.

-- enable over Interrupt Enable Register
addrmap_i.ISR.trigger.enable  <=;
-- as mask over Interrupt Mask Register
addrmap_i.ISR.trigger.enable  <= not;

3. As in spec, each interrupt register generates 1 bit output of logical or of all interrupt fields. This signal can be accessed in VHDL over intr filed.

po_irq(0) <= addrmap_o.ISR.intr;

4. IRQ Channel assignment to map file.
In systems where there is a possibility to have for more than one interrupt channel there is a need to propagate this information to a map file. This is not defined by the SystemRDL standard.
There is a custom property defined, similar to access channel one.
desyrdl_intr_channel = “0”;

If not set defaults to “0”. This value is visible in map file as INTERRUPT<value>

Edited by Lukasz Butkowski

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