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fix(tmpl): handle sparse registers correctly

Lukasz Butkowski requested to merge v_data_out into main

Registers can have multiple fields with gaps inbetween, e.g. bit 24 and bits 7..0 being used. The default assignment was assuming packed registers and forced the rest, bits 31..9 in this example, to zero, creating a conflict on bit 24.

Solve this by creating entity-wide signals for each field's data, then assign them to slices of the output vector in a single combinational process.

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