fix(top.vhd.in): fix index for multi-dim register arrays (!20) · Merge requests · FPGA Firmware / Tools / DesyRDL

The code was wrong.

I also double-checked the order of indexes. Assume the definition a 2D register array in SystemRDL like this:

reg {
  [..]
} multi_array[2][3] ;

Then systemrdl-compiler interprets the second range [3] as the one that iterates the most frequently [1]. desyrdl/DesyListener.py makes correct use of this. The VHDL signal also uses the order multi_array(idx_n,idx_m):

type t_addrmap_test_hectare_in is record
  [..]
  multi_array : t_reg_multi_array_3d_in(0 to 2-1, 0 to 3-1);
  [..]
end record;

This change fixes the VHDL generate block that instantiates the 2D register array. It was in accordance with this definition already, but had a bug.

[1] https://systemrdl-compiler.readthedocs.io/en/stable/api/node.html#systemrdl.node.AddressableNode.array_dimensions

fix(top.vhd.in): fix index for multi-dim register arrays

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