fix: drop top name from VHDL port assignment; fix VHDL typo

The VHDL record for the input port of dataframe.vhd does not have the top AddressMap node as a layer of hierarchy. Fix the port assignment accordingly.

Previously (wrong):

v_dataframe(63 downto 0) := pi_dataframe.columns.timestamp.f;

Expected:

v_dataframe(63 downto 0) := pi_dataframe.timestamp.f;