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DWC10 Support

Cagil Guemues requested to merge dwc10 into main

Changelog:

  • Add ability to work with DWC10
  • Add method to dut.py to change the front panel RJ45 connector values
  • RTM type now gets automatically understood by reading the magic number inside the FPGA
  • adc_dac_test now plots differently if DWC10 is selected

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