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feat: DMA Engine with AXI4-Stream Packetizer

Cagil Guemues requested to merge daq_integration into main

This introduces the AXI4-Stream packetizer. It takes a wide vector of input data that is constructed by a "dataframe" entity and streams it towards the BSP, where the AXI DMA entity receives it.

The "dataframe" entity is generated from "daq_dataframe.rdl" by an external daq-dataframe.py script.

AXI4-Stream Packetizer sends the output stream into the Xilinx-DMA Engine inside the BSP.

DMA engine converts S2MM and puts the data into the PL-DDR4. DMA engine uses Scatter-Gather(SG) Mode. CPU has an access to the BRAM which is used to store the Block Descriptors for the SG.

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