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MLVDS Bus Feature

Cagil Guemues requested to merge a7_m2s into main

This branch brings the major feature of controlling all 16 motors of the ZMX Crate. The main effort of this sprint was focusing on MLVDS-Bus implementation between the Manager and Subordinate ZMX connection modules.

Changelog:

  • Implement Manager-to-Subordinate(M2S) and Subordinate-to-Manager(S2M) paths. Basic functionality is proven to work on hardware however more long-term tests are needed.
  • Extend the Aurora frame structure to cover the Memory Mapped Interface (No logic to handle the MM, only there to pass the bytes across the Aurora link
  • Application configuration no longer configures DAQ
  • K7 <-> A7 Aurora link is no longer continuously active. It relies on strobes on both sides together with back-pressure
  • Entire ZMX Connection module logic now runs on a single clock domain (Aurora User clock) also for Subordinates
  • Timing Module now configures its register lengths using Application Configuration through C_TRG_CNT parameter
  • Improve overall documentation of the project

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