Draft: feat: Module HDL configuration is now done through Config parameters exported as HDL via FWK (!3) · Merge requests · FPGA Firmware / Modules / Miscellaneous Modules (MISC) / timing

Cagil Guemues requested to merge config into main Sep 17, 2024

This branch brings the feature of using Config variable on tcl as HDL configuration package.

The way how FWK handles Config variables are explained here: TODO Add FWK doc page URL once its merged.

Remove the generic ports. Timing now relies on the auto-generated pkg_timing_config.vhd file to configure itself (C_OUT_TRG_CNT and C_EXT_TRG_CNT)

Draft: feat: Module HDL configuration is now done through Config parameters exported as HDL via FWK

Merge request reports