feat: add interrupt registers ISR and IER, DesyRDL with intr (!2) · Merge requests · FPGA Firmware / Modules / Miscellaneous Modules (MISC) / timing

Lukasz Butkowski requested to merge add_interrupt_regs into main Jun 20, 2024

Adds ISR and IER interrupt registers. Allows to issue interrupt request on enabled triggers.

Requires DesyRDL > 1.4 with intr support.

feat: add interrupt registers ISR and IER, DesyRDL with intr