Tags

Tags give the ability to mark specific points in history as being important

1.1.0

529286a0 · refactor!: make register names compatible to new version · Jul 03, 2023
```
fcm_legacy 1.1.0 with removed WORD_ prefix
```
1.0.2

7e1bd09f · perf: separate FSM seq for boot V6, 7S and US, improves booting time · Nov 16, 2022
2.1.0

d2a7ebed · fix(phy): Virtex5 startup assign values to not used ports · Jul 28, 2022

2.0.0

84cecca2 · Merge branch 'systemrdl' into 'main' · Jun 02, 2022

Release 2.0.0

BREAKING CHANGE:

DesyRDL is now used for implementing register access. Use a recent fwk
(e.g. 0.7.1) and make sure to run `make install` when building locally,
so that DesyRDL gets installed into a project-local Python virtual
environment.

The bus interface is now AXI4-Lite instead of IBUS.

1.0.1

adc054f6 · Merge branch 'lf_line_endings' into 'master' · Feb 08, 2022
```
TMCB2 legacy
```
1.0.0

4fb5d06d · Issue #7907 : Changed namespace variable 'Interface' to accept 'axi' or... · Mar 17, 2021
```
2021 winter shutdown
```
0.1.0

284406af · Extended documentation, shortened address space name to FCM · Feb 12, 2021
```
Taken from SVN at revision r4366
```