fix: FIFO full after reset

With an AXI burst length of 4 on the DSBAM (Zynq Ultrascale+) the FIFO_STATUS registers started counting like crazy after programming the bitstream without DAQ regions enabled. It turned out that for the burst length of 4 the value for the almost full threshold of the FIFOs in the DAQ is set to 0, which led to the FIFO18E2 cells already setting the flag after the reset.

I suspect that the value 0 was not intended as a threshold. In any case, the DAQ works with this change. We should discuss whether this approach is correct or whether I have misunderstood something here.