Draft: WIP: feat: add GTY support (!1) · Merge requests · FPGA Firmware / Modules / Communication Busses Modules (BUS) / lll

Michael Buechler requested to merge ultrascale_gty into main Apr 04, 2024

The GTY interface is very similar and the same Ultrascale Transceiver Wizard is used to create an IP block. Unfortunately the MGT component has different port names:

gthrxp_in -> gtyrxp_in
gthrxn_in -> gtyrxn_in
gthtxp_out -> gtytxp_out
gthtxn_out -> gtytxn_out

Edited Apr 04, 2024 by Michael Buechler

Draft: WIP: feat: add GTY support

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