LLL Cleanup

Changelog:

• MAJOR Bug: AXI4-Lite bus for the application ACLK was not connected anymore after LLL changes. This is fixed now
• MAJOR Bug: Default BSP Configuration was disabling FCLK clock buffer for the PCIe. This is fixed.
• C_P2P configuration parameter renamed to C_LLL since Point-2-Point is something different than LLL. LLL uses also the SFP connector.
• LLL module is now added to the project if the user selects C_LLL = 1 (This required LLL_TOP to be wrapped)
• MGT_PLL logic should not be something optional since this is a common Board Feature. Removed C_MGT_PLL option from the bsp_configs
• Renamed bsp_config_81MHz to bsp_config_xfel since 81MHz doesn't really tell the full story of this BSP configuration. This is a breaking change for the Projects in terms of cfg naming! (llrf_fd project must be adjusted)
• PCIe IRQ Count is now fixed to 16. There is no reason why this should be dynamically changed by user.
• Code beautification on many parts. More comments, styling etc.
• BSP Configuration Identification is now properly injected into the BSP.ID register
• CLK_FREQ register size reduced.