fix(addr): always generate 32 bit wide SystemRDL memories

When fwk generates the equivalent of an IBUS address map definition in SystemRDL, a VII_AREA entry becomes an "external mem" instance.

When the size per element is 16 or less then too little memory range is reserved for it, and another node in the address tree can overlap with it. This is because the VHDL implementation addresses each element as 32 bits, so the address increments by 4 for each element. The SystemRDL definition should declare a memory with 32 bits per entry, while still having 16 bit data.

The problem is that the memwidth property cannot be changed to always be 32 without breaking the generated mapfiles, which rely on that property.

With this change, a virtual register is added to the memory. It has a single field with the correct data width. This shows up as a new line in the mapfile as e.g.:

PILEUP.1.AREA_COEF_TABLE.DATA

Issue: #10814