chore: update DesyRDL with multi-dim array fix
DesyRDL had a bug in the VHDL top.vhd template where ports of 2D register arrays are assigned. This change updates DesyRDL to that commit.
Related DesyRDL merge request: https://gitlab.msktools.desy.de/fpgafw/tools/desyrdl/-/merge_requests/20
Edited by Lukasz Butkowski