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FPGA Firmware
Firmware Framework
Commits
a646664d
Commit
a646664d
authored
3 years ago
by
Lukasz Butkowski
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feat(addr): include parameters in RDL top file from Config provided
parent
7630b162
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1 changed file
src/fwfwk_addr.tcl
+13
-2
13 additions, 2 deletions
src/fwfwk_addr.tcl
with
13 additions
and
2 deletions
src/fwfwk_addr.tcl
+
13
−
2
View file @
a646664d
...
...
@@ -388,13 +388,24 @@ proc ::fwfwk::addr::genRdlFromParent {AccessChannel Nodes Idx RdlFile GenHdl} {
dict for
{
id content
}
$Nodes
{
if
{[
dict get $content Parent
]
== $Idx
}
{
set properties
""
set Variables
[
dict get $content Variables
]
if
{
$Variables !=
""
}
{
foreach
{
prop val
}
$Variables
{
if
{
!
[
string is double -strict $val
]}
{
set val
"
\"
$val
\"
"
};
# put non numbers in double quote
if
{
$properties ==
""
}
{
set properties
".
${prop}
(
$val
)"
}
else
{
set properties
"
$properties
,.
${prop}
(
$val
)"
}
}
set properties
"#(
$properties
)"
# puts
"
$properties
"
}
set num
[
dict get $content Num
]
set identifier
[
dict get $content Id
]
if
{
$num ==
""
}
{
puts $RdlFile
"
[
dict get $content Name
]
$identifier
@
[
dict get $content BaseAddress
]
;"
puts $RdlFile
"
[
dict get $content Name
]
$properties
$identifier
@
[
dict get $content BaseAddress
]
;"
}
else
{
set stride
[
expr
{[
dict get $content AddressRange
]
+ 1
}]
puts $RdlFile
"
[
dict get $content Name
]
$identifier
\[
$num
\]
@
[
dict get $content BaseAddress
]
+=
$stride
;"
puts $RdlFile
"
[
dict get $content Name
]
$properties
$identifier
\[
$num
\]
@
[
dict get $content BaseAddress
]
+=
$stride
;"
}
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