Explore projects

In this tutorial, fwk is used to create a project that carries a module that interacts with DesyRDL and address spaces.

An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

A simple module to be used as a tutorial for fwk. It implements a simple counter in VHDL with Configuration parameters.

Millepede II is a package for linear least squares fits with a large number of parameters. Developed for the alignment and calibration of tracking detectors.