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An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

A simple module to be used as a tutorial for fwk. It implements a simple counter in VHDL with Configuration parameters.

Building blocks for the cooperative development of firmware and software.

BSP for DAMC-FMC2ZUP board

Decoder module for the timing information from timers.

Main VHDL library

Example project to test desyrdl with examples

A simplified version of the UNIO FMC board support package.

DRTM-PZT4 board support module