Explore projects

An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

A simple module to be used as a tutorial for fwk. It implements a simple counter in VHDL with Configuration parameters.

BSP for DAMC-FMC2ZUP board

Decoder module for the timing information from timers.

BSP for the DAMC-FMC1Z7IO board

Main VHDL library

Board support package for the RFSoC 4x2 kit.

Example project to test desyrdl with examples

A simplified version of the UNIO FMC board support package.

DRTM-PZT4 board support module

Single cavity simulator project that uses SIS8300-L2 with DWC8VM1 RTM board. It models a superconducting TESLA type cavity (electrical and mechanical model)