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Project to generate and maintain common FwkLinux package feed, mirrors and pr/hash services.

Test Project for the RFSoC 4x2 Kit.

In this tutorial, fwk is used to create a project that carries a module that interacts with DesyRDL and address spaces.

An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

A simple module to be used as a tutorial for fwk. It implements a simple counter in VHDL with Configuration parameters.

BSP for DAMC-FMC2ZUP board

Decoder module for the timing information from timers.

Main VHDL library

Example project to test desyrdl with examples

A simplified version of the UNIO FMC board support package.