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An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

Example project for DRTM-AD84 rtm. By default with FMC1Z7IO BSP.

Wing-LDA, all FPGAs and MARS module

A simplified version of the UNIO FMC board support package.

Decoder module for the timing information from timers.

Application Module for DRTM-DWC10 Rear Transition Module

This simple project shows how to use fwk projects with creating baremetal application using the Vitis Tool.

Board support package for the RFSoC 4x2 kit.

Project to generate and maintain common FwkLinux package feed, mirrors and pr/hash services.

BSP for DAMC-FMC2ZUP board

Verification for the llrf_fwd_refl_decoupler

Verification project for llrf_qldet