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An example module for tutorial purposes. This module is using .rdl files to describe its register space. It also instantiates another DESY Module (TIMING) and integrates its address space into itself.

Decoder module for the timing information from timers.

Application Module for DRTM-DWC10 Rear Transition Module

Wing-LDA, all FPGAs and MARS module

Verification Projects for components under desy_vhdl library

BSP for the DAMC-FMC1Z7IO board

Windows distributive of Dioptas software

Generic Timing Module. Creates triggers, strobes for the application.

FPGAs of the wing-LDA in separate directory

Project to generate and maintain common FwkLinux package feed, mirrors and pr/hash services.

CALICE AHCAL DIF2 firmware

Verification for the llrf_fwd_refl_decoupler

Example project for DRTM-AD84 rtm. By default with FMC1Z7IO BSP.