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A script to select either external(FTSW) or onboard clock source

Satoru Yamada requested to merge feature/select_different_clock_sources into master

Select either external(FTSW) or onboard clock source in program_plls_commandline function, which is called by initialize_pcie40.py

It was tested at B4 test bench by using initialiez_pcie40.py and worked fine.

Output messages of the program_plls_commandline():

When clksource = 2 for the argument is seletcted; Programing PLLs... cd /home/usr/yamadas/software/Scripts; source ./setup.sh; python -c "import pll_program; pll_program.program_plls_commandline(0,2)";cd - loading lli.mem_multi loading lli.i2c Before programming plls : Clock Up : OK Before programming plls : TTD Up : NO Use external(FTSW) clock source (F2 button in pll_status_small.py) ===== Hard resetting PLL SI5345_U23 ===== .... Done ................................................... ===== Programming PLL SI5345_U23====================== ..... Done ................................................... ===== Hard resetting PLL SI5345_U48 ===== .... Done ................................................... ===== Programming PLL SI5345_U48====================== ..... Done ................................................... ===== Hard resetting PLL SI5344_U54 ===== .... Done ................................................... ===== Programming PLL SI5344_U54====================== ..... Done ................................................... ..... wait to stabilize .................................. ..... ready .............................................. After programming plls : Clock Up : OK After programming plls : TTD Up : OK

When clksource = 2 for the argument is seletcted; Programing PLLs... cd /home/usr/yamadas/software/Scripts; source ./setup.sh; python -c "import pll_program; pll_program.program_plls_commandline(0,3)";cd - loading lli.mem_multi loading lli.i2c Before programming plls : Clock Up : OK Before programming plls : TTD Up : OK Use local clock source (F3 button in pll_status_small.py) ===== Hard resetting PLL SI5345_U23 ===== .... Done ................................................... ===== Programming PLL SI5345_U23====================== ..... Done ................................................... ===== Hard resetting PLL SI5345_U48 ===== .... Done ................................................... ===== Programming PLL SI5345_U48====================== ..... Done ................................................... ===== Hard resetting PLL SI5344_U54 ===== .... Done ................................................... ===== Programming PLL SI5344_U54====================== ..... Done ................................................... ..... wait to stabilize .................................. ..... ready .............................................. After programming plls : Clock Up : OK After programming plls : TTD Up : OK /home/usr/yamadas

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