Add functions to reset the b2link

Pcie40Libraries/Makefile

@@ -27,20 +27,20 @@ MINIPODS_OBJ=$(MINIPODS_SRC:%.c=$(OBJ_DIR)%.o)
 LTC2990_SRC= 
 LTC2990_OBJ=$(LTC2990_SRC:$(SRC_DIR)$(LTC2990_DIR)%.c=$(OBJ_DIR)%.o)
 
-# Belle II slow control library 
-B2SLC_SRC= pcie40_b2slc.c 
-B2SLC_OBJ=$(B2SLC_SRC:%.c=$(OBJ_DIR)%.o)
+# Belle II specific libraries (slow control, ECS, ...) 
+B2LIB_SRC= pcie40_b2slc.c pcie40_b2ecs.c
+B2LIB_OBJ=$(B2LIB_SRC:%.c=$(OBJ_DIR)%.o)
 
 # static libraries
 ECS_LIB= libecs.a
 MINIPODS_LIB= libminipods.a
 LTC2990_LIB= libltc2990.a
-B2SLC_LIB = libb2slc.a
+B2LIB_LIB = libb2pcie40.a
 
 # dynamic libraries
 LLI_DYNLIB= libpcie40.so
 
-all: $(ECS_OBJ) $(ECS_LIB) $(MINIPODS_OBJ) $(MINIPODS_LIB) $(LTC2990_OBJ) $(LTC2990_LIB) $(B2SLC_LIB) $(LLI_DYNLIB)
+all: $(ECS_OBJ) $(ECS_LIB) $(MINIPODS_OBJ) $(MINIPODS_LIB) $(LTC2990_OBJ) $(LTC2990_LIB) $(B2LIB_LIB) $(LLI_DYNLIB)
 
 $(ECS_OBJ): $(OBJ_DIR)%.o : %.c
 	@echo "Construction of ecs objects $@ from $<"
@@ -53,15 +53,15 @@ $(ECS_LIB) : $(ECS_OBJ)
 	ar -q $(LIB_DIR)$(ECS_LIB) $(ECS_OBJ)
 	@echo ""
 
-$(B2SLC_OBJ): $(OBJ_DIR)%.o : %.c
+$(B2LIB_OBJ): $(OBJ_DIR)%.o : %.c
 	@echo "Construction of ecs objects $@ from $<"
 	mkdir -p obj
 	$(CC) $(CFLAGS) -I . -I $(PCIE40_INC_DIR)  $< -o $@	
 
-$(B2SLC_LIB) : $(B2SLC_OBJ)
+$(B2LIB_LIB) : $(B2LIB_OBJ)
 	@echo "Construction of Belle II SLC Library"
 	mkdir -p lib
-	ar -q $(LIB_DIR)$(B2SLC_LIB) $(B2SLC_OBJ)
+	ar -q $(LIB_DIR)$(B2LIB_LIB) $(B2LIB_OBJ)
 	@echo ""
 
 $(MINIPODS_OBJ): $(OBJ_DIR)%.o : $(SRC_DIR)%.c
@@ -87,7 +87,7 @@ $(LTC2990_LIB) : $(LTC2990_OBJ)
 $(LLI_DYNLIB) : $(ECS_OBJ) $(MINIPODS_OBJ)
 	@echo "Construction of dynamic LLI technical Library for V2"
 	mkdir -p lib
-	$(CC) -o $(LIB_DIR)$(LLI_DYNLIB) -shared $(ECS_OBJ) $(PLL_OBJ) $(MINIPODS_OBJ) $(B2SLC_OBJ) -L $(PCIE40_DYN_LIB) -lpcie40driver_ecs
+	$(CC) -o $(LIB_DIR)$(LLI_DYNLIB) -shared $(ECS_OBJ) $(PLL_OBJ) $(MINIPODS_OBJ) $(B2LIB_OBJ) -L $(PCIE40_DYN_LIB) -lpcie40driver_ecs
 	@echo 
 
 clean: mrproper

Pcie40Libraries/pcie40_b2ecs.c

+// File for Belle 2 ECS functions for PCIe40
+#include "pcie40_b2ecs.h"
+#include "pcie40_ecs.h"
+
+// **************************************************************************
+// Status of the b2link: 0 = BAD, 1 = GOOD
+// **************************************************************************
+int pcie40_b2linkstatus(int fd) { 
+  int ret = 0 ;
+  ret = ecs_read( fd , ECS_BAR , ECS_B2LINK_STATUS_ADD ) ;
+  return ( ( ret & ( 1 << ECS_B2LINK_STATUS_BIT ) ) 
+	   >> ECS_B2LINK_STATUS_BIT ) ;
+}
+
+// **************************************************************************
+// Resynchronize the b2link, returns 1 if success, 0 if error 
+// **************************************************************************
+int pcie40_resyncb2link(int fd) { 
+  int ret = 0 ;
+  int i ; 
+  for ( i = 0 ; i<10 ; i++ ) {
+    ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD , 0x0 ) ;
+    if ( 0 == ret ) return ret ;
+    ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD , 
+		     1 << ECS_B2LINK_RESET_BIT ) ;
+    if ( 0 == ret ) return ret ;
+    ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD , 0x0 ) ;
+    if ( 0 == ret ) return ret ;
+    ret = pcie40_b2linkstatus( fd ) ;
+    if ( 1 == ret ) return ret ;
+  }    
+
+  return 0;
+}
+

Pcie40Libraries/pcie40_b2ecs.h

+#ifndef PCIE40_B2ECS_H
+#define PCIE40_B2ECS_H
+// Header file for Belle 2 ECS functions with PCIe40
+
+// Constants
+// BAR number for Slow control interface
+#define ECS_BAR 2
+// Address of the register to reset the write FIFO and bit to use
+#define ECS_B2LINK_RESET_ADD 0x00050100
+#define ECS_B2LINK_RESET_BIT 2
+#define ECS_B2LINK_STATUS_ADD 0x00050120
+#define ECS_B2LINK_STATUS_BIT 2
+
+// Functions to read/write registers and stream files to Front End
+
+/// b2link status (1 = OK, 0= BAD)
+int pcie40_b2linkstatus(int fd);
+
+/// Resynchronize b2link
+int pcie40_resyncb2link(int fd);
+#endif // PCIE40_B2ECS_H