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Commit e32c8398 authored by Patrick Robbe's avatar Patrick Robbe
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Add argument to specify the link number

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Pcie40Applications/main_pcie40_b2linkreset.c
+ 1
− 1
View file @ e32c8398
......@@ -5,7 +5,7 @@
int main(int argc, char *argv[]) {
ecs_open( 0 , 2 ) ;
int result = 0;
result = pcie40_resyncb2link( 0 ) ;
result = pcie40_resyncb2link( 0 , 0 ) ;
ecs_close( 0 , 2 ) ;
if ( 0 == result )
......
Pcie40Applications/main_pcie40_b2slc.c
+ 1
− 1
View file @ e32c8398
......@@ -5,7 +5,7 @@
int main(int argc, char *argv[]) {
ecs_open( 0 , 2 ) ;
int result = pcie40_readfee32( 0 , 0x12 ) ;
int result = pcie40_readfee32( 0 , 0 , 0x12 ) ;
ecs_close( 0 , 2 ) ;
......
Pcie40Libraries/pcie40_b2ecs.c
+ 6
− 6
View file @ e32c8398
......@@ -6,29 +6,29 @@
// **************************************************************************
// Status of the b2link: 0 = BAD, 1 = GOOD
// **************************************************************************
int pcie40_b2linkstatus(int fd) {
int pcie40_b2linkstatus(int fd, int link) {
int ret = 0 ;
ret = ecs_read( fd , ECS_BAR , ECS_B2LINK_STATUS_ADD ) ;
return ( ( ret & ( 1 << ECS_B2LINK_STATUS_BIT ) )
>> ECS_B2LINK_STATUS_BIT ) ;
return ( ( ret & ( 1 << ( ECS_B2LINK_STATUS_BIT + link ) ) )
>> ( ECS_B2LINK_STATUS_BIT + link ) ) ;
}
// **************************************************************************
// Resynchronize the b2link, returns 1 if success, 0 if error
// **************************************************************************
int pcie40_resyncb2link(int fd) {
int pcie40_resyncb2link(int fd , int link ) {
int ret = 0 ;
int i ;
for ( i = 0 ; i<10 ; i++ ) {
ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD , 0x0 ) ;
if ( 0 != ret ) return 0 ;
ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD ,
1 << ECS_B2LINK_RESET_BIT ) ;
1 << ( ECS_B2LINK_RESET_BIT + link ) ) ;
if ( 0 != ret ) return 0 ;
ret = ecs_write( fd , ECS_BAR , ECS_B2LINK_RESET_ADD , 0x0 ) ;
if ( 0 != ret ) return 0 ;
usleep( 1000000 );
ret = pcie40_b2linkstatus( fd ) ;
ret = pcie40_b2linkstatus( fd , link ) ;
if ( 1 == ret ) return ret ;
}
......
Pcie40Libraries/pcie40_b2ecs.h
+ 6
− 6
View file @ e32c8398
......@@ -6,16 +6,16 @@
// BAR number for Slow control interface
#define ECS_BAR 2
// Address of the register to reset the write FIFO and bit to use
#define ECS_B2LINK_RESET_ADD 0x00050100
#define ECS_B2LINK_RESET_BIT 2
#define ECS_B2LINK_STATUS_ADD 0x00050120
#define ECS_B2LINK_STATUS_BIT 2
#define ECS_B2LINK_RESET_ADD 0x00050240
#define ECS_B2LINK_RESET_BIT 0
#define ECS_B2LINK_STATUS_ADD 0x000500E0
#define ECS_B2LINK_STATUS_BIT 0
// Functions to read/write registers and stream files to Front End
/// b2link status (1 = OK, 0= BAD)
int pcie40_b2linkstatus(int fd);
int pcie40_b2linkstatus(int fd, int link);
/// Resynchronize b2link
int pcie40_resyncb2link(int fd);
int pcie40_resyncb2link(int fd, int link);
#endif // PCIE40_B2ECS_H
Pcie40Libraries/pcie40_b2slc.c
+ 39
− 39
View file @ e32c8398
......@@ -7,7 +7,7 @@
readfee8
returns -1 in case of error
\* ---------------------------------------------------------------------- */
int pcie40_readfee8( int dev , int adr) {
int pcie40_readfee8( int dev , int link , int adr) {
// PCIe40
if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
// Reset the FIFO (Emit and reception)
......@@ -25,25 +25,25 @@ int pcie40_readfee8( int dev , int adr) {
int data_word_4 = 0x000c ;
int data_word_5 = 0xEEEE ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_4 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_5 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// start emit
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_EMIT_BIT ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_START_ADD ,
1 << ( SLC_WFIFO_EMIT_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -52,14 +52,14 @@ int pcie40_readfee8( int dev , int adr) {
int i ;
for ( i=0 ; i<10 ; i++ ) {
usleep( 10 ) ; //10 ms
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS ) ;
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS + link * 0x40 ) ;
if ( ret == 1 ) break;
}
if (i == 10) return -1;
// Read the value
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD + link * 0x40 );
// check address consistency
if ( ( ( ret & 0x7F00 ) >> 8 ) != adr ) return -1 ;
......@@ -70,13 +70,13 @@ int pcie40_readfee8( int dev , int adr) {
//==============================================================================
// Write 8b
//==============================================================================
int pcie40_writefee8( int dev , int adr , int val ) {
int pcie40_writefee8( int dev , int link , int adr , int val ) {
// PCIe40
if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
// Reset the FIFO
unsigned ret = 0 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
1 << ( SLC_WFIFO_RESET_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -88,25 +88,25 @@ int pcie40_writefee8( int dev , int adr , int val ) {
int data_word_4 = 0x0000 | ( val & 0xFF ) ;
int data_word_5 = 0xEEEE ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_4 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_5 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// start emit
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_EMIT_BIT ) ;
1 << ( SLC_WFIFO_EMIT_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -117,7 +117,7 @@ int pcie40_writefee8( int dev , int adr , int val ) {
//==============================================================================
// Read 32b
//==============================================================================
unsigned long pcie40_readfee32( int dev , int adr ) {
unsigned long pcie40_readfee32( int dev , int link , int adr ) {
// PCIe40
if ( ( adr <0 ) || ( adr > 0xFFFF ) ) return -1 ;
// Reset the FIFO
......@@ -134,22 +134,22 @@ unsigned long pcie40_readfee32( int dev , int adr ) {
int data_word_3 = 0x7000 | ( adr & 0xFF ) ;
int data_word_5 = 0xEEEE ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_5 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// start emit
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_EMIT_BIT ) ;
1 << ( SLC_WFIFO_EMIT_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -158,15 +158,15 @@ unsigned long pcie40_readfee32( int dev , int adr ) {
int i ;
for ( i=0 ; i<10 ; i++ ) {
usleep( 10 ) ; //10 ms
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS ) ;
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS + link * 0x40 ) ;
if ( ret == 4 ) break;
}
if (i == 10) return -1;
// Read the value
int ret1 = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
int ret2 = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
int ret1 = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD + link * 0x40 );
int ret2 = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD + link * 0x40 );
int add1 = ( ret1 & 0x7F000000 ) >> 24 ;
int add2 = ( ret1 & 0x7F00 ) >> 8 ;
......@@ -187,13 +187,13 @@ unsigned long pcie40_readfee32( int dev , int adr ) {
//==============================================================================
// Write 32b
//==============================================================================
int pcie40_writefee32( int dev , int adr , int val ) {
int pcie40_writefee32( int dev , int link , int adr , int val ) {
// PCIe40
if ( ( adr <0 ) || ( adr > 0xFFFF ) ) return -1 ;
// Reset the FIFO
unsigned ret = 0 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
1 << ( SLC_WFIFO_RESET_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -214,34 +214,34 @@ int pcie40_writefee32( int dev , int adr , int val ) {
int data_word_8 = 0xEEEE ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_4 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_5 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_6 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_7 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD ,
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD + link * 0x40 ,
(int) ( data_word_8 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// start emit
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_EMIT_BIT ) ;
1 << ( SLC_WFIFO_EMIT_BIT + link ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
......@@ -249,6 +249,6 @@ int pcie40_writefee32( int dev , int adr , int val ) {
return ret;
}
int pcie40_writestream( int dev , char * filename ) {
int pcie40_writestream( int dev , int link , char * filename ) {
return 0 ;
}
Pcie40Libraries/pcie40_b2slc.h
+ 10
− 9
View file @ e32c8398
......@@ -6,24 +6,25 @@
// BAR number for Slow control interface
#define SLC_BAR 2
// Address of the register to reset the write FIFO and bit to use
#define SLC_WFIFO_RESET_ADD 0x00050100
#define SLC_WFIFO_RESET_ADD 0x00050200
#define SLC_WFIFO_RESET_BIT 8
#define SLC_WFIFO_START_ADD 0x00050260
#define SLC_WFIFO_EMIT_BIT 0
#define SLC_WFIFO_ADD 0x00050000
#define SLC_RFIFO_STATUS 0x00050160
#define SLC_RFIFO_ADD 0x00050140
#define SLC_WFIFO_ADD 0x00060000
#define SLC_RFIFO_STATUS 0x00060100
#define SLC_RFIFO_ADD 0x00060120
// Functions to read/write registers and stream files to Front End
int pcie40_readfee8(int fd, int adr);
int pcie40_readfee8(int fd, int link, int adr);
int pcie40_writefee8(int fd, int adr, int val);
int pcie40_writefee8(int fd, int link, int adr, int val);
unsigned long pcie40_readfee32(int fd, int adr);
unsigned long pcie40_readfee32(int fd, int link , int adr);
int pcie40_writefee32(int fd, int adr, int val);
int pcie40_writefee32(int fd, int link , int adr, int val);
int pcie40_writestream(int fd, char *filename);
int pcie40_writestream(int fd, int link , char *filename);
#endif // PCIE40_B2SLC_H
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