Add lock for PLL functions

.gitignore

@@ -42,7 +42,7 @@ Pcie40Applications/pcie40_send_ul
 DumpFifo.txt
 Pcie40Applications/pcie40_dmatest
 Pcie40Applications/pcie40_dmahighrate
-Pcie40Applications/regconfig
-Pcie40Applications/statlink
-Pcie40Applications/timediff
+Pcie40Applications/pcie40_regconfig
+Pcie40Applications/pcie40_statlink
+Pcie40Applications/pcie40_timediff
 data_file.txt

Scripts/pll_status_small.py

@@ -13,6 +13,7 @@ import sys
 import pathtocomponents
 import curses
 import math
+import fcntl
 
 from fpga_comp import Arria10
 from si534x_comp import Si534x
@@ -23,6 +24,15 @@ from mpodCmd import enableChannel
 from ltc2990_comp import Ltc2990
 import addresses_comp as add
 
+class Pll_Locker:
+    def __enter__ (self):
+        self.fp = open("/tmp/pcie40_pll_lockfile.lck",'w+')
+        fcntl.flock(self.fp.fileno(), fcntl.LOCK_EX)
+
+    def __exit__ (self, _type, value, tb):
+        fcntl.flock(self.fp.fileno(), fcntl.LOCK_UN)
+        self.fp.close()
+
 temp_counter = 0 
 
 ## mapping of TX minipods
@@ -598,9 +608,10 @@ def draw_menu(stdscr, dev):
         # cursor_y = min (height - 1, cursor_y)
 
         # Refresh windows with pll information
-        pll_window(pll_si5345_1, devices[1], fpga, freq[1], conf[1], win2)
-        pll_window(pll_si5345_2, devices[2], fpga, freq[2], conf[2], win3)
-        pll_window(pll_si5344  , devices[3], fpga, freq[3], conf[3], win4)
+        with Pll_Locker():
+            pll_window(pll_si5345_1, devices[1], fpga, freq[1], conf[1], win2)
+            pll_window(pll_si5345_2, devices[2], fpga, freq[2], conf[2], win3)
+            pll_window(pll_si5344  , devices[3], fpga, freq[3], conf[3], win4)
         temperature_window(ltc1, ltc2, ltc3, win8)
         fanout_window(fpga, win5)
         link_window( fpga , win7 )