add extra frame for pcie40_b2slc

Pcie40Applications/main_pcie40_b2slc.cpp

@@ -28,8 +28,16 @@ bool USE_FEE32       = false;
 bool READ_ONLY       = false;
 bool WRITE           = false;
 bool STREAM          = false;
+bool OP_FLAG         = false;
 char *filename;
+char *operation;
 
+/* defined address */
+#define PCIE40_CHECKFEE 0x102  //address needed from firmware
+#define REG_FEEHWTYPE   0x0
+#define REG_FEESERIAL   0x0
+#define REG_FEEFWTYPE   0x0
+#define REG_FEEFWVER    0x0
 
 void argument(int argc, char **argv){
 
@@ -67,6 +75,10 @@ void argument(int argc, char **argv){
       STREAM = true;
       filename = argv[++i];
     } 
+    if(ss=="--op"){
+      OP_FLAG = true;
+      operation = argv[++i];
+    }
     if(ss=="--h" || ss=="-help"){
       fprintf(stderr,  "./pcie40_b2slc --dev 0 --ch 0 --fee32 --w 0x12 0x0\n"
                        "--dev   xx              #device slot number which installed PCIe40\n" 
@@ -81,43 +93,145 @@ void argument(int argc, char **argv){
   }
 }
 
+/* ---------------------------------------------------------------------- *\
+   hsreg
+\* ---------------------------------------------------------------------- */
+int
+hsreg(const char *name)
+{
+  static struct { char *name; int adrs; } regs[] = {
+    { "checkfee", PCIE40_CHECKFEE },
+    
+    /*{ "trghold",  PCIE40_TRGOFF },
+    { "trigger",  PCIE40_TRGON },
+    { "realtrg",  PCIE40_TTTRG },
+    { "simtrg" ,  PCIE40_DUMTRG },
+    { "simple",   PCIE40_SUPMODE },
+    { "verbose",  PCIE40_RAWMODE },
+    
+    { "supmode",  PCIE40_SUPMODE },
+    { "rawmode",  PCIE40_RAWMODE },
+    
+    { "pdstl",    PCIE40_PDSTL },
+    { "pdstlall", PCIE40_PDSTLALL },
+    { "adcth",    PCIE40_ADCTH },
+    { "tdcth",    PCIE40_TDCTH },
+    { "delay",    PCIE40_DELAY },
+    { "window",   PCIE40_WINDOW },
+
+    { "stat",     HSREGL_STAT },*/
+  };
+  int i;
+
+  if (isdigit(name[0])) {
+    return strtoul(name, 0, 16);
+  }
+
+  for (i = 0; i<sizeof(regs)/sizeof(regs[0]); i++) {
+    if (strcmp(regs[i].name, name) == 0) {
+      return regs[i].adrs;
+    }
+  }
+    
+  i = strtoul(name, 0, 16);
+  return (i > 0 && i < 0x100) ? i : -1;
+}
 
+int checkfee(int dev, int ch){
+  int ret;
+  int hwtype;
+  int serial;
+  int fwtype;
+  int fwver;
+  static const char *feetype[] = {
+    "UNDEF", "SVD", "CDC", "BPID", "EPID", "ECL", "EECL", "KLM", "EKLM",
+    "TRG", "UNKNOWN-10", "UNKNOWN-11",
+    "UNKNOWN-12", "UNKNOWN-13", "DEMO", "TEST" };
+  static const char *demotype[] = {
+    "UNDEF", "HSLB-B2L", "SP605-B2L", "ML605-B2L", "AC701-B2L" };
+  static const char *trgtype[] = {
+    "TRGMERGER", /* = 0 */
+    "TRGTSF",    /* = 1 */
+    "TRG2D",     /* = 2 */
+    "TRG3D",     /* = 3 */
+    "TRGNN",     /* = 4 */
+    "TRGEVTT",   /* = 5 */
+    "TRGGRL",    /* = 6 */
+    "TRGGDL",    /* = 7 */
+    "TRGETM",    /* = 8 */
+    "TRGTOP",    /* = 9 */
+    "TRGKLM",    /* = 10 */
+  };
+
+
+  hwtype = pcie40_readfee8(dev, ch, REG_FEEHWTYPE);
+  serial = pcie40_readfee8(dev, ch, REG_FEESERIAL);
+  fwtype = pcie40_readfee8(dev, ch, REG_FEEFWTYPE);
+  fwver  = pcie40_readfee8(dev, ch, REG_FEEFWVER);
+
+  serial |= (hwtype & 0xf) << 8;
+  fwver  |= (fwtype & 0xf) << 8;
+  hwtype = (hwtype >> 4) & 0xf;
+  fwtype = (fwtype >> 4) & 0xf;
+
+  if (hwtype == 14 && fwtype > 0 && fwtype <= 4) {
+    printf("FEE type %s serial %d version %d at PCIE40_LINK-%d\n",
+	   demotype[fwtype], serial, fwver, ch);
+  } else if (hwtype == 9 && fwtype >= 0 && fwtype <= 10) {
+    printf("FEE type %s serial %d version %d at PCIE40_LINK-%d\n",
+	   trgtype[fwtype], serial, fwver, ch);
+  } else {
+    printf("FEE type %s serial %d firmware %d version %d at PCIE40_LINK-%d\n",
+	   feetype[hwtype], serial, fwtype, fwver, ch);
+  }
+    
+  return 0;
+}
 
 int main(int argc, char** argv){
   
+  // parse arguments
   argument(argc, argv);
 
-
+  // open pcie40 device driver for current process
   ecs_open( dev_slot , SLC_BAR );
 
   int result = -1;
+
   if(USE_FEE8 && READ_ONLY){
     result = pcie40_readfee8( dev_slot , ch , addr );
     printf("reg%04x = %08x\n", addr, result);
   }else if(USE_FEE8 && WRITE){
     result = pcie40_writefee8( dev_slot , ch , addr, data );
     if(result == 0)
-      printf("Write %04x to register %04x\n", data, addr);
+      printf("Write 0x%04x to register 0x%04x\n", data, addr);
     else
-      printf("Failed to write %04x to register %04x\n", data, addr);
+      printf("ERROR: Failed to write 0x%04x to register 0x%04x\n", data, addr);
   }else if(USE_FEE32 && READ_ONLY){
     result = pcie40_readfee32( dev_slot , ch , addr );
     printf("reg%04x = %08x\n", addr, result);
   }else if(USE_FEE32 && WRITE){
     result = pcie40_writefee32( dev_slot , ch , addr, data );
     if(result == 0)
-      printf("Write %08x to register %04x\n", data, addr);
+      printf("Write 0x%08x to register 0x%04x\n", data, addr);
     else
-      printf("Failed to write %08x to register %04x\n", data, addr);
+      printf("ERROR: Failed to write 0x%08x to register %04x\n", data, addr);
   }else if(STREAM){
     result = pcie40_writestream( dev_slot , ch , filename ) ;
     if(result == 0)
       std::cerr<<"Succeed streaming file: " << filename << std::endl;
     else
-      std::cerr<<"Failed streaming file: " << filename << std::endl;
-    //std::cout << filename << std::endl; 
+      std::cerr<<"ERROR: Failed streaming file: " << filename << std::endl;
   } 
 
+  //This is only frame for register operation in the furture
+  if(OP_FLAG){
+    unsigned int inter_addr = hsreg( operation );
+    if(inter_addr == PCIE40_CHECKFEE)
+      checkfee(dev_slot, ch);
+  }
+
+  // close pcie40 device driver for current process
   ecs_close( dev_slot , SLC_BAR) ;
 
   return 0 ;