add extren{} back to include files

Pcie40DriverLibraries/ecs_driverlib.h

@@ -3,6 +3,10 @@
 
 #include <stdint.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 //dg`wt.pcie40.c.ecs` In order to interact with the ECS interface of the PCIe40 driver, C libraries are provided (*libpcie40_ecs.so* and *libpcie40_ecs.a*).
 // To use these libraries, add ``#include <lhcb/pcie40/ecs.h>`` to your source code and ``-lpcie40_ecs`` to your linker flags.
 // This API is very simple, consisting only of a handful of functions to create I/O memory mappings and to access individual I/O registers, see <<PCIe40 driver ECS API>>.
@@ -33,5 +37,8 @@ uint32_t p40_ecs_r32(uint32_t volatile *regs, uint32_t addr);//?>
 //>`regs` Pointer populated by `p40_ecs_open` .
 //>`addr` Address of register.
 
+#ifdef __cplusplus
+} //extern "C"
+#endif
 
 #endif//__PCIE40_ECS_H

Pcie40Libraries/pcie40_b2config.h

@@ -9,6 +9,9 @@
 #define SIZE_MEMO_FPGA 1024
 
 // Functions to read/write registers and stream files to Front End
+#ifndef USE_PCIE40
+extern "C" {
+#endif 
   /// returns the FPGA firmware's version number
   std::string pcie40_fpgaVersion(int dev);
   /// Disable one TX link (physically via the minipod configuration)
@@ -43,5 +46,8 @@
   /// Reset of Out of Frequency counter
   void pcie40_pllFrequencyReset( int dev , int pll ) ;
 
+#ifndef USE_PCIE40
+}
+#endif
 
 #endif // PCIE40_B2CONFIG_H

Pcie40Libraries/pcie40_b2slc.h

@@ -20,6 +20,9 @@
 #define SLC_RFIFO_ADD 0x00060000
 
 // Functions to read/write registers and stream files to Front End
+#ifndef USE_PCIE40
+extern "C" {
+#endif 
 int pcie40_readfee8(int dev, int ch, int adr);
 
 int pcie40_writefee8(int dev, int ch, int adr, int val);
@@ -34,6 +37,9 @@ int pcie40_writestream( int dev , int ch , char *filename , const char * detecto
 
 int pcie40_writebytestream(int dev, int ch, int len, const char *bytes);
 
+#ifndef USE_PCIE40
+}
+#endif 
 
 #endif // PCIE40_B2SLC_H
 

Pcie40Libraries/pcie40_reg.h

@@ -14,6 +14,12 @@
 #include <string.h>
 #include <iostream>
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+#if defined(__dummy_close_bracket_to_cheat_emacs_auto_indent)
+}
+#endif
 
 #define SLC_BAR 2
 
@@ -299,5 +305,13 @@ feename(int hwtype, int fwtype)
     return ringbuf[i];
   }
 }
+
+#if defined(__dummy_open_bracket_to_cheat_emacs_auto_indent)
+__dummy_open_bracket_to_cheat_emacs_auto_indent {
+#endif
+#if defined(__cplusplus)
+}
+#endif
+
 #endif /* __PCIE40REG_H__ */