Add individual FIFO resets (firmware version >= 8.2)

Pcie40Libraries/pcie40_b2slc.cpp

@@ -28,8 +28,23 @@ int pcie40_readFifoFillLevel( int dev , int ch ) {
 
 int pcie40_resetWriteFifo( int dev , int ch ) { 
   unsigned ret = 0 ;
+  unsigned wle = 0 ; 
+  // wait that the FIFO are empty
+  int i ;
+  for ( i=0 ; i<10 ; i++ ) {
+    usleep( 10 ) ; //10 ms
+    wle = pcie40_writeFifoFillLevel( dev , ch ) ; 
+    if ( wle == 0 ) break;
+  }
+
+  if (i == 10) {
+    printf( "Timeout reset write\n" ) ;
+  }
+
+  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
+  if ( ret != 0 ) return -1 ;
   ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 
-       1 << SLC_WFIFO_RESET_BIT ) ;
+		   1 << ( SLC_WFIFO_RESET_BIT + ch ) ) ;
   if ( ret != 0 ) return -1 ;
   ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
   if ( ret != 0 ) return -1 ;
@@ -39,24 +54,24 @@ int pcie40_resetWriteFifo( int dev , int ch ) {
 int pcie40_resetReadFifo( int dev , int ch ) { 
   unsigned ret = 0 ;
   unsigned rle = 0 ; 
-  unsigned wle = 0 ; 
   // wait that the FIFO are empty
   int i ;
   for ( i=0 ; i<10 ; i++ ) {
     usleep( 10 ) ; //10 ms
     rle = pcie40_readFifoFillLevel( dev , ch ) ; 
-    wle = pcie40_writeFifoFillLevel( dev , ch ) ; 
-    if ( ( rle == 0 ) && ( wle == 0 ) ) break;
+    if ( rle == 0 ) break;
   }
 
   if (i == 10) {
-    printf( "Timeout\n" ) ;
+    printf( "Timeout reset read\n" ) ;
   }
-  
-  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 
-       1 << SLC_WFIFO_RESET_BIT ) ;
+
+  ret = ecs_write( dev , SLC_BAR , SLC_RFIFO_RESET_ADD , 0 ) ;
+  if ( ret != 0 ) return -1 ;  
+  ret = ecs_write( dev , SLC_BAR , SLC_RFIFO_RESET_ADD , 
+		   1 << ( SLC_RFIFO_RESET_BIT + ch ) ) ;
   if ( ret != 0 ) return -1 ;
-  ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
+  ret = ecs_write( dev , SLC_BAR , SLC_RFIFO_RESET_ADD , 0 ) ;
   if ( ret != 0 ) return -1 ;
   return ret ;
 }
@@ -116,9 +131,9 @@ int pcie40_readData( int dev , int ch , std::vector< int > & result , int length
 int pcie40_readfee8( int dev , int ch , int adr) {
   // PCIe40
   if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
-  // Reset the FIFO (Emit and reception)
+  // Reset the FIFO (Emit)
   unsigned ret = 0 ;
-  ret = pcie40_resetReadFifo( dev , ch ) ;
+  ret = pcie40_resetWriteFifo( dev , ch ) ;
   if ( ret != 0 ) return ret ;
 
   // Fill the FIFO with the requested information: write MSB first
@@ -132,6 +147,10 @@ int pcie40_readfee8( int dev , int ch , int adr) {
   ret = pcie40_writeToFifo( dev , ch , data ) ;
   if ( ret != 0 ) return ret ;
 
+  // reset read FIFO
+  ret = pcie40_resetReadFifo( dev , ch ) ;
+  if ( ret != 0 ) return ret ;
+
   // start emit
   ret = pcie40_startEmit( dev , ch ) ;
   if ( ret != 0 ) return -1 ;
@@ -160,7 +179,7 @@ int pcie40_writefee8( int dev , int ch , int adr , int val ) {
   if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
   // Reset the FIFO
   unsigned ret = 0 ;
-  ret = pcie40_resetReadFifo( dev , ch ) ;
+  ret = pcie40_resetWriteFifo( dev , ch ) ;
   if ( ret != 0 ) return ret ;
 
   // Fill the FIFO with the requested information: write MSB first
@@ -188,7 +207,7 @@ unsigned long pcie40_readfee32( int dev , int ch , int adr ) {
   if ( ( adr <0 ) || ( adr > 0xFFFF ) ) return -1 ;
   // Reset the FIFO
   unsigned ret = 0 ;
-  ret = pcie40_resetReadFifo( dev , ch ) ;
+  ret = pcie40_resetWriteFifo( dev , ch ) ;
   if ( ret != 0 ) return ret ;
 
   // Fill the FIFO with the requested information: write MSB first
@@ -201,6 +220,10 @@ unsigned long pcie40_readfee32( int dev , int ch , int adr ) {
   ret = pcie40_writeToFifo( dev , ch , data ) ;
   if ( ret != 0 ) return ret ;
 
+  // reset read FIFO
+  ret = pcie40_resetReadFifo( dev , ch ) ;
+  if ( ret != 0 ) return ret ;
+
   // start emit
   ret = pcie40_startEmit( dev , ch ) ;
   if ( ret != 0 ) return -1 ;
@@ -278,7 +301,7 @@ int pcie40_writefee32( int dev , int ch , int adr , int val ) {
   if ( ( adr <0 ) || ( adr > 0xFFFF ) ) return -1 ;
   // Reset the FIFO
   unsigned ret = 0 ;
-  ret = pcie40_resetReadFifo( dev , ch ) ;
+  ret = pcie40_resetWriteFifo( dev , ch ) ;
   if ( ret != 0 ) return ret ;
 
   int val1 = ( val & 0xFF ) ;
@@ -318,7 +341,7 @@ int pcie40_writestream( int dev , int ch , char * filename ) {
   }
   // Reset the FIFO
   unsigned ret = 0 ;
-  ret = pcie40_resetReadFifo( dev , ch ) ;
+  ret = pcie40_resetWriteFifo( dev , ch ) ;
 
   if ( ret != 0 ) { 
     fclose( fp ) ; 

Pcie40Libraries/pcie40_b2slc.h

@@ -6,8 +6,10 @@
 // BAR number for Slow control interface
 #define SLC_BAR 2
 // Address of the register to reset the write FIFO and bit to use
-#define SLC_WFIFO_RESET_ADD 0x00050400
-#define SLC_WFIFO_RESET_BIT 8
+#define SLC_WFIFO_RESET_ADD 0x00050560
+#define SLC_WFIFO_RESET_BIT 0
+#define SLC_RFIFO_RESET_ADD 0x000505a0
+#define SLC_RFIFO_RESET_BIT 0
 #define SLC_WFIFO_START_ADD 0x00050480
 #define SLC_WFIFO_EMIT_BIT 0
 #define SLC_WFIFO_ADD 0x00060000

Scripts/testSLC.py

@@ -20,8 +20,8 @@ nerr = 0
 
 for i in xrange( args.N ):
     data = random.randint( 0 , 0xFFFFFFFF )
-    lli.pcie40_writefee32( 0 , args.channel , 0x17 , data )
-    result = slc_read( 0 , args.channel , 0x17 )
+    lli.pcie40_writefee32( 0 , args.channel , 0x12 , data )
+    result = slc_read( 0 , args.channel , 0x12 )
     if result != data:
         print("mismatch between write ({0:X}) and read ({1:X})".format( data , result ))  
         nerr = nerr + 1