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Commit 682c3481 authored by Patrick Robbe's avatar Patrick Robbe
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Add per link information

parent 62272789
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......@@ -579,13 +579,26 @@ class Arria10(object):
status, val = mem.read( self.dev , 0x00050000 )
return ( val & 0x1 ) >> 0
def rxReadyIndividual(self, i):
status, val = mem.read( self.dev , 0x00050060 )
return ( val & ( 0x1 << i ) ) >> i
def txReady(self):
status, val = mem.read( self.dev , 0x00050000 )
return ( val & 0x2 ) >> 1
def txReadyIndividual(self, i):
status, val = mem.read( self.dev , 0x00050060 )
return ( val & ( 0x10 << i ) ) >> ( i + 4 )
def b2linkReady(self):
status, val = mem.read( self.dev , 0x00050000 )
return ( val & 0x4 ) >> 2
def b2linkReadyIndividual(self, i):
status, val1 = mem.read( self.dev , 0x000500C0 )
status, val2 = mem.read( self.dev , 0x000500E0 )
return ( ( ( val1 & ( 0x1 << i ) ) >> i ) & ( ( val2 & ( 0x1 << i ) ) >> i ) )
def resynchronizeLink(self):
mem.write( self.dev , 0x00050100 , 0x0 )
......
......@@ -128,20 +128,23 @@ def fanout_window(fpga, win):
win.addstr(4,19,'{0:5d}'.format(fpga.triggerCounter()),GREEN)
win.addstr(5,1,'RX ready : ' , curses.A_BOLD)
if fpga.rxReady() == 1:
win.addstr(5,12, 'OK' , GREEN )
else:
win.addstr(5,12,'NO',RED)
win.addstr(5,16,'TX ready : ' , curses.A_BOLD)
if fpga.txReady() == 1:
win.addstr(5,27, 'OK' , GREEN )
else:
win.addstr(5,27,'NO',RED)
win.addstr(5,31,'b2link ready : ' , curses.A_BOLD)
if fpga.b2linkReady() == 1:
win.addstr(5,46, 'OK' , GREEN )
else:
win.addstr(5,46,'NO',RED)
for link in range( 4 ):
if fpga.rxReadyIndividual(link) == 1:
win.addstr(5,12+3*link, 'OK' , GREEN )
else:
win.addstr(5,12+3*link,'NO',RED)
win.addstr(5,25,'TX ready : ' , curses.A_BOLD)
for link in range( 4 ):
if fpga.txReadyIndividual(link) == 1:
win.addstr(5,36+3*link, 'OK' , GREEN )
else:
win.addstr(5,36+3*link,'NO',RED)
win.addstr(5,50,'b2link ready : ' , curses.A_BOLD)
for link in range( 4 ):
if fpga.b2linkReadyIndividual( link ) == 1:
win.addstr(5,65+3*link, 'OK' , GREEN )
else:
win.addstr(5,65+3*link,'NO',RED)
win.refresh()
......
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