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Commit 5a62b350 authored by Patrick Robbe's avatar Patrick Robbe
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Add functions for 32b read

parent b8d7e426
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Pcie40Libraries/pcie40_b2slc.c
+ 102
− 14
View file @ 5a62b350
......@@ -12,17 +12,24 @@ int pcie40_readfee8( int dev , int adr) {
if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
// Reset the FIFO
unsigned ret = 0 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 0 ) ;
if ( ret != 0 ) return -1 ;
// Fill the FIFO with the requested information
// Fill the FIFO with the requested information: write MSB first
int data_word_1 =
( 0x73 ) | ( 0x07 << 8 ) | ( adr << 16 ) | ( 0x0c << 24 ) ;
int data_word_2 = ( 0x08 << 0 ) ;
// (temporary : 32 bits only)
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word_1 & 0xFFFFFFFF ) ) ;
int data_word_2 = ( 0x08 ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
return 0 ;
// Wait for the result to come back
int i ;
......@@ -40,38 +47,67 @@ int pcie40_readfee8( int dev , int adr) {
return ret;
}
//==============================================================================
// Write 8b
//==============================================================================
int pcie40_writefee8( int dev , int adr , int val ) {
if ( ( adr <= 0 ) || ( adr > 0x7F ) ) return -1 ;
int ret ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
if ( ret != 0 ) return -1 ;
int data_word_1 =
( 0x73 ) | ( 0x0a << 8 ) | ( adr << 16 ) | ( ( val & 0xFF ) << 24 ) ;
int data_word_2 = ( 0x08 << 0 ) ;
// (temporary : 32 bits only)
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , (int) ( data_word_1 & 0xFFFFFFFF ) ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
(int) ( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
(int) ( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
return 0 ;
}
//==============================================================================
// Read 32b
//==============================================================================
int pcie40_readfee32( int dev , int adr , int *valp ) {
// PCIe40
if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
// Reset the FIFO
unsigned ret = 0 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD , 1 << SLC_WFIFO_RESET_BIT ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
if ( ret != 0 ) return -1 ;
// Fill the FIFO with the requested information
int data_word_1 =
( 0x73 ) | ( 0x0c << 8 ) | ( ( adr & 0xFF ) << 16 ) | ( ( ( adr & 0xFF00 ) >> 8 ) << 24 ) ;
int data_word_2 = ( 0x08 << 24 ) | ( 0x02 << 16 ) | ( 0x0c0c ) ;
( 0x73 ) | ( 0x0c << 8 ) | ( ( adr & 0xFF ) << 16 ) |
( ( ( adr & 0xFF00 ) >> 8 ) << 24 ) ;
int data_word_2 = ( 0x04 << 24 ) | ( 0x04 << 16 ) | ( 0x0c0c ) ;
//
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
int data_word_3 =
( 0x73 ) | ( 0x0c << 8 ) | ( 0x0c << 16 ) | ( 0x0c << 24 ) ;
int data_word_4 = ( 0x08 << 24 ) | ( 0x02 << 16 ) | ( 0x0c0c ) ;
//
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD , ( data_word_1 & 0xFFFFFFFF ) |
( ( data_word_2 & 0xFFFFFFFF ) >> 32 ) ) ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
( data_word_4 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// Wait for the result to come back
......@@ -90,8 +126,60 @@ int pcie40_readfee32( int dev , int adr , int *valp ) {
return ret;
}
//==============================================================================
// Read 32b
//==============================================================================
int pcie40_writefee32( int dev , int adr , int val ) {
return 0 ;
// PCIe40
if ( ( adr <=0 ) || ( adr > 0x7F ) ) return -1 ;
// Reset the FIFO
unsigned ret = 0 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_RESET_ADD ,
1 << SLC_WFIFO_RESET_BIT ) ;
if ( ret != 0 ) return -1 ;
// Fill the FIFO with the requested information
int data_word_1 =
( 0x73 ) | ( 0x0b << 8 ) | ( ( adr & 0xFF ) << 16 ) |
( ( ( adr & 0xFF00 ) >> 8 ) << 24 ) ;
int data_word_2 = ( 0x04 << 24 ) | ( 0x04 << 16 )
| ( val & 0xFF ) | ( ( ( val & 0xFF00 ) >> 8 ) << 8 );
//
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
( data_word_1 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
( data_word_2 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
int data_word_3 =
( 0x73 ) | ( 0x0c << 8 ) | ( ( ( val & 0xFF0000 ) >> 16 ) << 16 ) |
( ( (val & 0xFF000000 ) >> 24 ) << 24 ) ;
int data_word_4 = ( 0x08 << 24 ) | ( 0x02 << 16 ) | ( 0x0c0c ) ;
//
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_MSB ,
( data_word_3 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
ret = ecs_write( dev , SLC_BAR , SLC_WFIFO_ADD_LSB ,
( data_word_4 & 0xFFFFFFFF ) ) ;
if ( ret != 0 ) return -1 ;
// Wait for the result to come back
int i ;
for ( i=0 ; i<10 ; i++ ) {
usleep( 10 ) ; //10 ms
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_STATUS ) ;
if ( ret == 0x11 ) break;
}
if (i == 10) return -1;
// Read the value
ret = ecs_read( dev , SLC_BAR , SLC_RFIFO_ADD );
return ret;
}
int pcie40_writestream( int dev , char * filename ) {
......
Pcie40Libraries/pcie40_b2slc.h
+ 2
− 1
View file @ 5a62b350
......@@ -8,7 +8,8 @@
// Address of the register to reset the write FIFO and bit to use
#define SLC_WFIFO_RESET_ADD 0x00050100
#define SLC_WFIFO_RESET_BIT 8
#define SLC_WFIFO_ADD 0x00050000
#define SLC_WFIFO_ADD_MSB 0x000501F0
#define SLC_WFIFO_ADD_LSB 0x00050000
#define SLC_RFIFO_STATUS 0x00000
#define SLC_RFIFO_ADD 0x0000
......
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