Add driver files

Driver/pcie40_driver/common.h

+#ifndef __PCIE40_DRIVER_COMMON_H
+#define __PCIE40_DRIVER_COMMON_H
+//p40driver``+
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/version.h>
+
+#include "pcie40_dma_regmap.h"
+
+#ifndef P40_FMT
+#error "#define P40_FMT before including this file"
+#endif
+#define P40_DRV_NAME "lhcb_pcie40"
+#define P40_INFO KERN_INFO P40_FMT
+#define P40_WARN KERN_WARNING P40_FMT
+#define P40_DIAG KERN_DEBUG P40_FMT
+#define P40_ERR  KERN_ERR P40_FMT
+#define P40_PARM __FUNCTION__
+
+#define P40_MAX_BAR 3
+
+#define P40_COMMON_BARS_MASK ((1<<1)) //BAR1
+
+#define PCI_MAX_ALLOC (4*1024*1024) //0x20000
+
+//+`pcie40_state`
+struct pcie40_state {
+  struct list_head list;
+  struct pci_dev *pci_dev;
+
+  unsigned long bar_start[P40_MAX_BAR];
+  unsigned long bar_size[P40_MAX_BAR];
+
+  int link_id; //0 or 1
+  int dev_id; //unique device identifier, even for all link 0s, odd for all link 1s
+
+#ifndef PCIE40_EMU
+  void __iomem *bar0_regs;
+  void __iomem *bar1_regs;
+#else
+  void *bar0_regs;
+  void *bar1_regs;
+  void *bar2_regs;
+#endif
+
+  struct pcie40_ecs_state *ecs_state;
+  struct pcie40_daq_state *daq_state;
+  struct pcie40_cvp_state *cvp_state;
+};
+
+static inline uint32_t pcie40_read32_bar0(struct pcie40_state *common, unsigned long offset)
+{
+#ifndef PCIE40_EMU
+  return ioread32(common->bar0_regs + offset);
+#else
+  return *(uint32_t *)(common->bar0_regs + offset);
+#endif
+}
+
+static inline void pcie40_write32_bar0(struct pcie40_state *common, unsigned long offset, uint32_t value)
+{
+#ifndef PCIE40_EMU
+  iowrite32(value, common->bar0_regs + offset);
+#else
+  *(uint32_t *)(common->bar0_regs + offset) = value;
+#endif
+}
+
+static inline uint32_t pcie40_read32_ctrl(struct pcie40_state *common, unsigned long offset)
+{
+#ifndef PCIE40_EMU
+  return ioread32(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#else
+  return *(uint32_t *)(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#endif
+}
+
+static inline void pcie40_write32_ctrl(struct pcie40_state *common, unsigned long offset, uint32_t value)
+{
+#ifndef PCIE40_EMU
+  iowrite32(value, common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#else
+  *(uint32_t *)(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset) = value;
+#endif
+}
+
+static inline int pcie40_device_accessible(struct pcie40_state *common)
+{
+  uint32_t version = pcie40_read32_ctrl(common, P40_DMA_CTRL_OFF_VERSION);
+  return version != 0xFFFFFFFF;
+}
+
+/*
+static int pcie40_dev_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+  add_uevent_var(env, "DEVMODE=%#o", 0666);
+  return 0;
+}
+*/
+static inline char *pcie40_devnode(struct device *dev, umode_t *mode)
+{
+  if (mode) {
+    *mode = 0666;
+  }
+  return NULL;
+}
+
+int pcie40_setup_cdev(struct class *cls, struct cdev *cdev, dev_t dev_num, int minor, int bar, const char *dev_name, int dev_id, struct file_operations *fops);
+
+#endif//__PCIE40_DRIVER_COMMON_H