add lane_up to statlink

Pcie40Applications/statlink.cpp

@@ -249,8 +249,9 @@ statlink(std::bitset<48> link_mask, pcie40reg_t pcie40reg[])
       }
     }
     printf("%s", prompt);
-    printf("b2l=%s (rx=%s tx=%s rxsta=%s txsta=%s mask=%s)\n",
+    printf("b2l=%s (gbt=%s rx=%s tx=%s rxsta=%s txsta=%s mask=%s)\n",
 	   pcie40_b2l_status(dev_slot, i)?"UP":"DOWN",
+	   pcie40_gbt_status(dev_slot, i)?"UP":"DOWN",
 	   pcie40_b2l_rxstatus(dev_slot, i)?"UP":"DOWN",
 	   pcie40_b2l_txstatus(dev_slot, i)?"UP":"DOWN",
 	   pcie40_b2l_rxready(dev_slot, i)?"READY":"NOT READY",

Pcie40Libraries/pcie40_reg.cpp

@@ -83,6 +83,20 @@ int pcie40_rxdata_error(int dev){
 // Belle2link dedicated
 //----------------------------------------------
 
+// Status of gbt specified by lane_up
+int pcie40_gbt_status(int dev, int ch){
+  int ret = -1;
+  if(ch >= 0 && ch <=23){
+    ret = ecs_read(dev, SLC_BAR,  SLC_B2LINK_LANEUP1);
+    return ( ( ret & ( 1 << ( SLC_BASE_BIT + ch ) ) ) 
+	     >> ( SLC_BASE_BIT + ch ));
+  }else if (ch >= 24 && ch <= 47 ){
+    ret = ecs_read(dev, SLC_BAR,  SLC_B2LINK_LANEUP2);
+    return ( ( ret & ( 1 << ( SLC_BASE_BIT + ch - 24 ) ) ) 
+	     >> ( SLC_BASE_BIT + ch - 24 ));
+  }
+  return -1;
+}
 // Status of b2l specified by link_ok
 int pcie40_b2l_status(int dev, int ch){
   int ret = -1;

Pcie40Libraries/pcie40_reg.h

@@ -39,12 +39,14 @@ extern "C" {
 #define SLC_B2LINK_CNTDOWN     0x000A0000  // buffer recent third words of rxdata [15 downto 0] + three charish {21 downto 16} 
 #define SLC_B2LINK_MONSTATUS   0x000A0010  // buffer recent two words of rxdata
 
-#define SLC_B2LINK_TIE_STATUS1 0x000501E0  // link up/down channel 0-23, 1 bit pre channel
-#define SLC_B2LINK_TIE_STATUS2 0x00050200  // link up/down channel 24-47, 1 bit pre channel
+#define SLC_B2LINK_TIE_STATUS1 0x000501E0  // tied link up/down channel 0-23, 1 bit pre channel
+#define SLC_B2LINK_TIE_STATUS2 0x00050200  // tied link up/down channel 24-47, 1 bit pre channel
 #define SLC_B2LINK_STATUS1     0x000502E0  // link up/down channel 0-23, 1 bit pre channel
 #define SLC_B2LINK_STATUS2     0x00050300  // link up/down channel 24-47, 1 bit pre channel
-#define SLC_B2LINK_MASK1       0x00050520  // link up/down channel 0-23, 1 bit pre channel
-#define SLC_B2LINK_MASK2       0x00050540  // link up/down channel 24-47, 1 bit pre channel
+#define SLC_B2LINK_LANEUP1     0x00050320  // lane up/down channel 0-23, 1 bit pre channel
+#define SLC_B2LINK_LANEUP2     0x00050340  // lane up/down channel 24-47, 1 bit pre channel
+#define SLC_B2LINK_MASK1       0x00050520  // mask info channel 0-23, 1 bit pre channel
+#define SLC_B2LINK_MASK2       0x00050540  // make info channel 24-47, 1 bit pre channel
 #define SLC_RFIFO_STATUS       0x00060010
 
 
@@ -53,6 +55,7 @@ extern "C" {
 #define SLC_TRGTAG_NUMBER      0x00050040
 
 
+int pcie40_gbt_status(int dev, int ch);
 int pcie40_b2l_status(int dev, int ch);
 int pcie40_b2l_tiestatus(int dev, int ch);
 int pcie40_b2l_txstatus(int dev, int ch);