New structure

Pcie40Driver/pcie40_dma_regmap.h

+// This output was generated by the following command:
+// ../common/regmap_cfg_to_h.tcl P40_ ../common/pcie40_dma_regmap.cfg
+// Do not edit this file manually, your changes will be overwritten by the generator.
+
+#ifndef P40_REGMAP_H
+#define P40_REGMAP_H
+  static const int P40_DMA_REGMAP_VERSION = 0x20170424;
+
+  static const int P40_DMA_CTRL_OFF_INBUF_SIZE = 0x0A0;
+  static const int P40_DMA_CTRL_OFF_META_EVID_HI = 0x034;
+  static const int P40_DMA_CTRL_OFF_VERSION = 0x008;
+  static const int P40_DMA_CTRL_OFF_MAIN_EVID_LO = 0x024;
+  static const int P40_DMA_CTRL_OFF_MAIN_MSI_CYCLES = 0x08C;
+  static const int P40_DMA_CTRL_OFF_CHOKE_LAST_FROM_EVID_HI = 0x0E0;
+  static const int P40_DMA_CTRL_OFF_CHOKE_LAST_CYCLES = 0x0D8;
+  static const int P40_DMA_CTRL_OFF_CHOKE_TOTAL_SINCE_EVID_LO = 0x0D0;
+  static const int P40_DMA_CTRL_OFF_CHOKE_TOTAL_CYCLES = 0x0CC;
+  static const int P40_DMA_CTRL_OFF_TRUNC_TOTAL_SINCE_EVID_HI = 0x0B4;
+  static const int P40_DMA_CTRL_OFF_CHOKE_LAST_TO_EVID_LO = 0x0E4;
+  static const int P40_DMA_CTRL_OFF_TRUNC_LAST_TO_EVID_HI = 0x0C8;
+  static const int P40_DMA_CTRL_OFF_TRUNC_THRES = 0x0A8;
+  static const int P40_DMA_CTRL_OFF_RWTEST = 0x000;
+  static const int P40_DMA_CTRL_OFF_PCIE_GEN = 0x080;
+  static const int P40_DMA_CTRL_OFF_INBUF_FILL = 0x0A4;
+  static const int P40_DMA_CTRL_OFF_CHIP_ID_LO = 0x044;
+  static const int P40_DMA_CTRL_OFF_LINK_ID = 0x00C;
+  static const int P40_DMA_CTRL_OFF_ERROR = 0x014;
+  static const int P40_DMA_CTRL_OFF_TRUNC_LAST_FROM_EVID_LO = 0x0BC;
+  static const int P40_DMA_CTRL_OFF_ODIN_EVID_LO = 0x03C;
+  static const int P40_DMA_CTRL_OFF_META_PACKING = 0x02C;
+  static const int P40_DMA_CTRL_OFF_RESET = 0x010;
+  static const int P40_DMA_CTRL_OFF_MAIN_EVID_HI = 0x028;
+  static const int P40_DMA_CTRL_BASE_DAQ_MAIN_STREAM = 0x100;
+  static const int P40_DMA_CTRL_OFF_META_MSI_BYTES = 0x090;
+  static const int P40_DMA_CTRL_OFF_MSI_MODE = 0x084;
+  static const int P40_DMA_CTRL_OFF_CHOKE_TOTAL_SINCE_EVID_HI = 0x0D4;
+  static const int P40_DMA_CTRL_OFF_MAIN_GEN_FIXED = 0x01C;
+  static const int P40_DMA_CTRL_OFF_CHOKE_LAST_TO_EVID_HI = 0x0E8;
+  static const int P40_DMA_CTRL_OFF_CHIP_ID_HI = 0x048;
+  static const int P40_DMA_CTRL_OFF_META_EVID_LO = 0x030;
+  static const int P40_DMA_CTRL_OFF_MAIN_GEN_CTL = 0x018;
+  static const int P40_DMA_CTRL_OFF_META_MSI_CYCLES = 0x094;
+  static const int P40_DMA_CTRL_OFF_CHOKE_LAST_FROM_EVID_LO = 0x0DC;
+  static const int P40_DMA_CTRL_OFF_TRUNC_LAST_FROM_EVID_HI = 0x0C0;
+  static const int P40_DMA_CTRL_OFF_TRUNC_LAST_CYCLES = 0x0B8;
+  static const int P40_DMA_CTRL_OFF_TRUNC_TOTAL_SINCE_EVID_LO = 0x0B0;
+  static const int P40_DMA_CTRL_OFF_TRUNC_TOTAL_CYCLES = 0x0AC;
+  static const int P40_DMA_CTRL_OFF_ODIN_EVID_HI = 0x040;
+  static const int P40_DMA_CTRL_OFF_TRUNC_LAST_TO_EVID_LO = 0x0C4;
+  static const int P40_DMA_CTRL_OFF_MAIN_RAW_MODE = 0x020;
+  static const int P40_DMA_CTRL_OFF_MAIN_MSI_BYTES = 0x088;
+  static const int P40_DMA_CTRL_OFF_META_MSI_BLOCKS = 0x098;
+  static const int P40_DMA_CTRL_OFF_REGMAP = 0x004;
+  static const int P40_DMA_CTRL_OFF_ODIN_GEN_CTL = 0x038;
+
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESCS_BUSY_LO = 0x24;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_BYTES = 0x0C;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESCS_FILL_HI = 0x1C;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESCS_BUSY_HI = 0x28;
+  static const int P40_DMA_DAQ_STREAM_OFF_HOST_BUF_WRITE_OFF = 0x2C;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESC_BYTES = 0x14;
+  static const int P40_DMA_DAQ_STREAM_OFF_HOST_BUF_READ_OFF = 0x30;
+  static const int P40_DMA_DAQ_STREAM_OFF_ENABLE = 0x00;
+  static const int P40_DMA_DAQ_STREAM_OFF_HOST_MAP_PAGES = 0x38;
+  static const int P40_DMA_DAQ_STREAM_OFF_FLUSH = 0x08;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESCS = 0x10;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESCS_FILL_LO = 0x18;
+  static const int P40_DMA_DAQ_STREAM_OFF_HOST_MAP_ENTRIES = 0x34;
+  static const int P40_DMA_DAQ_STREAM_OFF_FPGA_BUF_DESC_FILL_BYTES = 0x20;
+  static const int P40_DMA_DAQ_STREAM_OFF_READY = 0x04;
+
+  static const int P40_DMA_CTRL_QSYS_BASE = 0x1000;
+
+  static const int P40_DMA_DAQ_MAIN_STREAM_QSYS_BASE = 0x1100;
+
+  static const int P40_DMA_DAQ_MAIN_MAP_QSYS_BASE = 0x10000;
+
+  static const int P40_DMA_DAQ_MAIN_BUF_QSYS_BASE = 0x100000;
+
+  static const int P40_DMA_DAQ_META_STREAM_QSYS_BASE = 0x0400;
+
+  static const int P40_DMA_DAQ_META_MAP_QSYS_BASE = 0x20000;
+
+  static const int P40_DMA_DAQ_META_BUF_QSYS_BASE = 0x200000;
+
+#endif//P40_REGMAP_H

Pcie40Driver/pcie40_driver_common.c

+#define P40_FMT "P40:%s(): "
+
+#include "pcie40_driver_common.h"
+
+int pcie40_setup_cdev(struct class *cls, struct cdev *cdev, dev_t dev_num, int minor, int bar, const char *dev_name, int dev_id, struct file_operations *fops)
+{
+  int rc = 0;
+  char dev_name_full[16] = {0};
+
+  snprintf(dev_name_full, sizeof(dev_name_full), "pcie40_%d_%s", dev_id, dev_name);
+
+  printk(P40_DIAG "device_create /dev/%s BAR=%d MAJ=%d, MIN=%d\n", P40_PARM, dev_name_full, bar, MAJOR(dev_num), MINOR(dev_num)+minor);
+
+  if (device_create(cls, NULL, MKDEV(MAJOR(dev_num), MINOR(dev_num)+minor), NULL, dev_name_full) == NULL){
+    rc = -1;
+    printk(P40_DIAG "device_create()\n", P40_PARM);
+    goto err_device_create;
+  }
+  cdev_init(cdev, fops);
+
+  rc = cdev_add(cdev, MKDEV(MAJOR(dev_num), MINOR(dev_num)+minor), 1);
+  if (rc < 0){
+    printk(P40_DIAG "cdev_add()\n", P40_PARM);
+    goto err_cdev_add;
+  }
+  return 0;
+
+err_cdev_add:
+  device_destroy(cls, MKDEV(MAJOR(dev_num), MINOR(dev_num)+minor));
+err_device_create:
+//err_no_bar:
+  return rc;
+}

Pcie40Driver/pcie40_driver_common.h

+#ifndef __PCIE40_DRIVER_COMMON_H
+#define __PCIE40_DRIVER_COMMON_H
+//p40driver``+
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/version.h>
+
+#include "pcie40_dma_regmap.h"
+
+#ifndef P40_FMT
+#error "#define P40_FMT before including this file"
+#endif
+#define P40_DRV_NAME "pcie40"
+#define P40_INFO KERN_INFO P40_FMT
+#define P40_WARN KERN_WARNING P40_FMT
+#define P40_DIAG KERN_DEBUG P40_FMT
+#define P40_ERR  KERN_ERR P40_FMT
+#define P40_PARM __FUNCTION__
+
+#define P40_MAX_BAR 3
+
+#define P40_COMMON_BARS_MASK ((1<<1)) //BAR1
+
+#define PCI_MAX_ALLOC (4*1024*1024) //0x20000
+
+//+`pcie40_state`
+struct pcie40_state {
+  struct list_head list;
+  struct pci_dev *pci_dev;
+
+  unsigned long bar_start[P40_MAX_BAR];
+  unsigned long bar_size[P40_MAX_BAR];
+
+  int link_id; //0 or 1
+  int dev_id; //unique device identifier, even for all link 0s, odd for all link 1s
+
+#ifndef PCIE40_EMU
+  void __iomem *bar0_regs;
+  void __iomem *bar1_regs;
+#else
+  void *bar0_regs;
+  void *bar1_regs;
+  void *bar2_regs;
+#endif
+
+  struct pcie40_ecs_state *ecs_state;
+  struct pcie40_daq_state *daq_state;
+  struct pcie40_cvp_state *cvp_state;
+};
+
+static inline uint32_t pcie40_read32_bar0(struct pcie40_state *common, unsigned long offset)
+{
+#ifndef PCIE40_EMU
+  return ioread32(common->bar0_regs + offset);
+#else
+  return *(uint32_t *)(common->bar0_regs + offset);
+#endif
+}
+
+static inline void pcie40_write32_bar0(struct pcie40_state *common, unsigned long offset, uint32_t value)
+{
+#ifndef PCIE40_EMU
+  iowrite32(value, common->bar0_regs + offset);
+#else
+  *(uint32_t *)(common->bar0_regs + offset) = value;
+#endif
+}
+
+static inline uint32_t pcie40_read32_ctrl(struct pcie40_state *common, unsigned long offset)
+{
+#ifndef PCIE40_EMU
+  return ioread32(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#else
+  return *(uint32_t *)(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#endif
+}
+
+static inline void pcie40_write32_ctrl(struct pcie40_state *common, unsigned long offset, uint32_t value)
+{
+#ifndef PCIE40_EMU
+  iowrite32(value, common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset);
+#else
+  *(uint32_t *)(common->bar1_regs + P40_DMA_CTRL_QSYS_BASE + offset) = value;
+#endif
+}
+
+static inline int pcie40_device_accessible(struct pcie40_state *common)
+{
+  uint32_t version = pcie40_read32_ctrl(common, P40_DMA_CTRL_OFF_VERSION);
+  return version != 0xFFFFFFFF;
+}
+
+/*
+static int pcie40_dev_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+  add_uevent_var(env, "DEVMODE=%#o", 0666);
+  return 0;
+}
+*/
+static inline char *pcie40_devnode(struct device *dev, umode_t *mode)
+{
+  if (mode) {
+    *mode = 0666;
+  }
+  return NULL;
+}
+
+int pcie40_setup_cdev(struct class *cls, struct cdev *cdev, dev_t dev_num, int minor, int bar, const char *dev_name, int dev_id, struct file_operations *fops);
+
+#endif//__PCIE40_DRIVER_COMMON_H