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Dmytro Levit
Software
Commits
01449ef7
Commit
01449ef7
authored
5 years ago
by
Patrick Robbe
Browse files
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parent
3e37a12d
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2
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2 changed files
Python/components/fpga_comp.py
+45
-4
45 additions, 4 deletions
Python/components/fpga_comp.py
Scripts/pll_status_small.py
+42
-2
42 additions, 2 deletions
Scripts/pll_status_small.py
with
87 additions
and
6 deletions
Python/components/fpga_comp.py
+
45
−
4
View file @
01449ef7
#!/usr/bin/python
#!/usr/bin/python
# -*- coding: utf8 -*-
"""
"""
fpga_comp.py -- module to query and set registers managed by the fpga
fpga_comp.py -- module to query and set registers managed by the fpga
...
@@ -552,6 +551,51 @@ class Arria10(object):
...
@@ -552,6 +551,51 @@ class Arria10(object):
return
json
.
loads
(
string
)
return
json
.
loads
(
string
)
def
runNumber
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050180
)
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
def
triggerTag
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x000501C0
)
return
(
val
&
0xFF00
)
>>
8
|
(
val
&
0x00FF
)
<<
8
def
clockUp
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x800
)
>>
11
def
ttdUp
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x1000
)
>>
12
def
triggerType
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x1E000
)
>>
13
def
triggerCounter
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x1FFE0000
)
>>
17
def
rxReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x1
)
>>
0
def
txReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x2
)
>>
1
def
b2linkReady
(
self
):
status
,
val
=
mem
.
read
(
self
.
dev
,
0x00050120
)
return
(
val
&
0x4
)
>>
2
def
resynchronizeLink
(
self
):
mem
.
write
(
self
.
dev
,
0x00050100
,
0x0
)
mem
.
write
(
self
.
dev
,
0x00050100
,
0x4
)
mem
.
write
(
self
.
dev
,
0x00050100
,
0x0
)
def
resetTriggerCounter
(
self
):
mem
.
write
(
self
.
dev
,
0x00050100
,
0x0
)
mem
.
write
(
self
.
dev
,
0x00050100
,
0x2
)
mem
.
write
(
self
.
dev
,
0x00050100
,
0x0
)
def
main
():
def
main
():
"""
Main function
"""
Main function
...
@@ -593,8 +637,5 @@ def main():
...
@@ -593,8 +637,5 @@ def main():
print
fpga
.
read_rx_ready
(
0
,
4
)
print
fpga
.
read_rx_ready
(
0
,
4
)
print
fpga
.
read_rx_ready
(
0
,
5
)
print
fpga
.
read_rx_ready
(
0
,
5
)
if
__name__
==
"
__main__
"
:
if
__name__
==
"
__main__
"
:
main
()
main
()
This diff is collapsed.
Click to expand it.
Scripts/pll_status_small.py
+
42
−
2
View file @
01449ef7
...
@@ -107,6 +107,42 @@ def fanout_window(fpga, win):
...
@@ -107,6 +107,42 @@ def fanout_window(fpga, win):
win
.
addstr
(
"
Warning : frequency out of range
"
,
YELLOW
)
win
.
addstr
(
"
Warning : frequency out of range
"
,
YELLOW
)
else
:
else
:
win
.
addstr
(
str
(
frequency_read
)
+
"
Hz
"
,
GREEN
)
win
.
addstr
(
str
(
frequency_read
)
+
"
Hz
"
,
GREEN
)
win
.
addstr
(
3
,
1
,
'
Run number :
'
,
curses
.
A_BOLD
)
win
.
addstr
(
3
,
14
,
'
{0:4d}
'
.
format
(
fpga
.
runNumber
()),
GREEN
)
win
.
addstr
(
3
,
20
,
'
Trigger tag :
'
,
curses
.
A_BOLD
)
win
.
addstr
(
3
,
34
,
'
{0:5d}
'
.
format
(
fpga
.
triggerTag
())
,
GREEN
)
win
.
addstr
(
3
,
40
,
'
Clock Up :
'
,
curses
.
A_BOLD
)
if
fpga
.
clockUp
()
==
1
:
win
.
addstr
(
3
,
51
,
'
OK
'
,
GREEN
)
else
:
win
.
addstr
(
3
,
51
,
'
NO
'
,
RED
)
win
.
addstr
(
3
,
55
,
'
TTD Up :
'
,
curses
.
A_BOLD
)
if
fpga
.
ttdUp
()
==
1
:
win
.
addstr
(
3
,
64
,
'
OK
'
,
GREEN
)
else
:
win
.
addstr
(
3
,
64
,
'
NO
'
,
RED
)
win
.
addstr
(
3
,
68
,
'
Trigger type :
'
,
curses
.
A_BOLD
)
win
.
addstr
(
3
,
83
,
'
{0:2d}
'
.
format
(
fpga
.
triggerType
()),
GREEN
)
win
.
addstr
(
4
,
1
,
'
Trigger counter :
'
,
curses
.
A_BOLD
)
win
.
addstr
(
4
,
19
,
'
{0:5d}
'
.
format
(
fpga
.
triggerCounter
()),
GREEN
)
win
.
addstr
(
5
,
1
,
'
RX ready :
'
,
curses
.
A_BOLD
)
if
fpga
.
rxReady
()
==
1
:
win
.
addstr
(
5
,
12
,
'
OK
'
,
GREEN
)
else
:
win
.
addstr
(
5
,
12
,
'
NO
'
,
RED
)
win
.
addstr
(
5
,
16
,
'
TX ready :
'
,
curses
.
A_BOLD
)
if
fpga
.
txReady
()
==
1
:
win
.
addstr
(
5
,
27
,
'
OK
'
,
GREEN
)
else
:
win
.
addstr
(
5
,
27
,
'
NO
'
,
RED
)
win
.
addstr
(
5
,
31
,
'
b2link ready :
'
,
curses
.
A_BOLD
)
if
fpga
.
b2linkReady
()
==
1
:
win
.
addstr
(
5
,
46
,
'
OK
'
,
GREEN
)
else
:
win
.
addstr
(
5
,
46
,
'
NO
'
,
RED
)
win
.
refresh
()
win
.
refresh
()
def
program_plls
(
plls
,
devices
,
files
,
win
):
def
program_plls
(
plls
,
devices
,
files
,
win
):
...
@@ -299,6 +335,8 @@ def draw_menu(stdscr, dev):
...
@@ -299,6 +335,8 @@ def draw_menu(stdscr, dev):
win6
.
box
()
win6
.
box
()
win6
.
addstr
(
1
,
1
,
"
F2: Program PLLs (source = FTSW), F3: Program PLLs (source = Osci.)
"
,
CYAN
|
curses
.
A_BOLD
)
win6
.
addstr
(
1
,
1
,
"
F2: Program PLLs (source = FTSW), F3: Program PLLs (source = Osci.)
"
,
CYAN
|
curses
.
A_BOLD
)
win6
.
addstr
(
2
,
1
,
"
F4: Clear LOS/OOF/LOL Flag, F5 : Hard reset, F6: Soft reset
"
,
CYAN
|
curses
.
A_BOLD
)
win6
.
addstr
(
2
,
1
,
"
F4: Clear LOS/OOF/LOL Flag, F5 : Hard reset, F6: Soft reset
"
,
CYAN
|
curses
.
A_BOLD
)
win6
.
addstr
(
3
,
1
,
"
F8: Resynchronize b2link, F9: Reset trigger counter
"
,
CYAN
|
curses
.
A_BOLD
)
win6
.
refresh
()
win6
.
refresh
()
# Loop where k is the last character pressed
# Loop where k is the last character pressed
...
@@ -401,8 +439,10 @@ def draw_menu(stdscr, dev):
...
@@ -401,8 +439,10 @@ def draw_menu(stdscr, dev):
line
=
line
+
1
line
=
line
+
1
col
=
col
+
x_max
/
3
col
=
col
+
x_max
/
3
line
=
3
line
=
3
elif
k
==
curses
.
KEY_F8
:
fpga
.
resynchronizeLink
()
elif
k
==
curses
.
KEY_F9
:
fpga
.
resetTriggerCounter
()
# cursor_x = max (0, cursor_x)
# cursor_x = max (0, cursor_x)
# cursor_x = min (width - 1, cursor_x)
# cursor_x = min (width - 1, cursor_x)
...
...
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Click to expand it.
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